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rovkarovka
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Serialize numWaveDispatch regs
1 parent e0042c9 commit 040b791

8 files changed

+34
-0
lines changed

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -728,6 +728,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
728728
MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
729729
HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
730730
HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
731+
NumWaveDispatchSGPRs(MFI.getNumWaveDispatchSGPRs()),
732+
NumWaveDispatchVGPRs(MFI.getNumWaveDispatchVGPRs()),
731733
HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
732734
Occupancy(MFI.getOccupancy()),
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ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
@@ -784,6 +786,8 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields(
784786
WaveLimiter = YamlMFI.WaveLimiter;
785787
HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
786788
HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
789+
NumWaveDispatchSGPRs = YamlMFI.NumWaveDispatchSGPRs;
790+
NumWaveDispatchVGPRs = YamlMFI.NumWaveDispatchVGPRs;
787791
BytesInStackArgArea = YamlMFI.BytesInStackArgArea;
788792
ReturnsVoid = YamlMFI.ReturnsVoid;
789793
IsWholeWaveFunction = YamlMFI.IsWholeWaveFunction;

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -270,6 +270,8 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
270270
bool WaveLimiter = false;
271271
bool HasSpilledSGPRs = false;
272272
bool HasSpilledVGPRs = false;
273+
uint16_t NumWaveDispatchSGPRs = 0;
274+
uint16_t NumWaveDispatchVGPRs = 0;
273275
uint32_t HighBitsOf32BitAddress = 0;
274276

275277
// TODO: 10 may be a better default since it's the maximum.
@@ -327,6 +329,8 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
327329
YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
328330
YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
329331
YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
332+
YamlIO.mapOptional("numWaveDispatchSGPRs", MFI.NumWaveDispatchSGPRs, false);
333+
YamlIO.mapOptional("numWaveDispatchVGPRs", MFI.NumWaveDispatchVGPRs, false);
330334
YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
331335
StringValue("$private_rsrc_reg"));
332336
YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,

‎llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
; CHECK-NEXT: waveLimiter: false
1818
; CHECK-NEXT: hasSpilledSGPRs: false
1919
; CHECK-NEXT: hasSpilledVGPRs: false
20+
; CHECK-NEXT: numWaveDispatchSGPRs: 0
21+
; CHECK-NEXT: numWaveDispatchVGPRs: 0
2022
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
2123
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
2224
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
@@ -287,6 +289,8 @@
287289
; CHECK-NEXT: waveLimiter: false
288290
; CHECK-NEXT: hasSpilledSGPRs: false
289291
; CHECK-NEXT: hasSpilledVGPRs: false
292+
; CHECK-NEXT: numWaveDispatchSGPRs: 0
293+
; CHECK-NEXT: numWaveDispatchVGPRs: 0
290294
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
291295
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
292296
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'

‎llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,8 @@
1616
; AFTER-PEI-NEXT: waveLimiter: false
1717
; AFTER-PEI-NEXT: hasSpilledSGPRs: true
1818
; AFTER-PEI-NEXT: hasSpilledVGPRs: false
19+
; AFTER-PEI-NEXT: numWaveDispatchSGPRs: 0
20+
; AFTER-PEI-NEXT: numWaveDispatchVGPRs: 0
1921
; AFTER-PEI-NEXT: scratchRSrcReg: '$sgpr68_sgpr69_sgpr70_sgpr71'
2022
; AFTER-PEI-NEXT: frameOffsetReg: '$fp_reg'
2123
; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32'

‎llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
; CHECK-NEXT: waveLimiter: false
1818
; CHECK-NEXT: hasSpilledSGPRs: false
1919
; CHECK-NEXT: hasSpilledVGPRs: false
20+
; CHECK-NEXT: numWaveDispatchSGPRs: 0
21+
; CHECK-NEXT: numWaveDispatchVGPRs: 0
2022
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
2123
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
2224
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'

‎llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
; CHECK-NEXT: waveLimiter: false
1818
; CHECK-NEXT: hasSpilledSGPRs: false
1919
; CHECK-NEXT: hasSpilledVGPRs: false
20+
; CHECK-NEXT: numWaveDispatchSGPRs: 0
21+
; CHECK-NEXT: numWaveDispatchVGPRs: 0
2022
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
2123
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
2224
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'

‎llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
# FULL-NEXT: waveLimiter: true
1818
# FULL-NEXT: hasSpilledSGPRs: false
1919
# FULL-NEXT: hasSpilledVGPRs: false
20+
# FULL-NEXT: numWaveDispatchSGPRs: 0
21+
# FULL-NEXT: numWaveDispatchVGPRs: 0
2022
# FULL-NEXT: scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11'
2123
# FULL-NEXT: frameOffsetReg: '$sgpr12'
2224
# FULL-NEXT: stackPtrOffsetReg: '$sgpr13'
@@ -127,6 +129,8 @@ body: |
127129
# FULL-NEXT: waveLimiter: false
128130
# FULL-NEXT: hasSpilledSGPRs: false
129131
# FULL-NEXT: hasSpilledVGPRs: false
132+
# FULL-NEXT: numWaveDispatchSGPRs: 0
133+
# FULL-NEXT: numWaveDispatchVGPRs: 0
130134
# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'
131135
# FULL-NEXT: frameOffsetReg: '$fp_reg'
132136
# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
@@ -206,6 +210,8 @@ body: |
206210
# FULL-NEXT: waveLimiter: false
207211
# FULL-NEXT: hasSpilledSGPRs: false
208212
# FULL-NEXT: hasSpilledVGPRs: false
213+
# FULL-NEXT: numWaveDispatchSGPRs: 0
214+
# FULL-NEXT: numWaveDispatchVGPRs: 0
209215
# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'
210216
# FULL-NEXT: frameOffsetReg: '$fp_reg'
211217
# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
@@ -286,6 +292,8 @@ body: |
286292
# FULL-NEXT: waveLimiter: false
287293
# FULL-NEXT: hasSpilledSGPRs: false
288294
# FULL-NEXT: hasSpilledVGPRs: false
295+
# FULL-NEXT: numWaveDispatchSGPRs: 0
296+
# FULL-NEXT: numWaveDispatchVGPRs: 0
289297
# FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg'
290298
# FULL-NEXT: frameOffsetReg: '$fp_reg'
291299
# FULL-NEXT: stackPtrOffsetReg: '$sp_reg'

‎llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,8 @@
2020
; CHECK-NEXT: waveLimiter: false
2121
; CHECK-NEXT: hasSpilledSGPRs: false
2222
; CHECK-NEXT: hasSpilledVGPRs: false
23+
; CHECK-NEXT: numWaveDispatchSGPRs: 0
24+
; CHECK-NEXT: numWaveDispatchVGPRs: 0
2325
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
2426
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
2527
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
@@ -80,6 +82,8 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
8082
; CHECK-NEXT: waveLimiter: false
8183
; CHECK-NEXT: hasSpilledSGPRs: false
8284
; CHECK-NEXT: hasSpilledVGPRs: false
85+
; CHECK-NEXT: numWaveDispatchSGPRs: 3
86+
; CHECK-NEXT: numWaveDispatchVGPRs: 1
8387
; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
8488
; CHECK-NEXT: frameOffsetReg: '$fp_reg'
8589
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
@@ -144,6 +148,8 @@ define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 {
144148
; CHECK-NEXT: waveLimiter: false
145149
; CHECK-NEXT: hasSpilledSGPRs: false
146150
; CHECK-NEXT: hasSpilledVGPRs: false
151+
; CHECK-NEXT: numWaveDispatchSGPRs: 16
152+
; CHECK-NEXT: numWaveDispatchVGPRs: 0
147153
; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
148154
; CHECK-NEXT: frameOffsetReg: '$sgpr33'
149155
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
@@ -200,6 +206,8 @@ define void @function() {
200206
; CHECK-NEXT: waveLimiter: false
201207
; CHECK-NEXT: hasSpilledSGPRs: false
202208
; CHECK-NEXT: hasSpilledVGPRs: false
209+
; CHECK-NEXT: numWaveDispatchSGPRs: 16
210+
; CHECK-NEXT: numWaveDispatchVGPRs: 0
203211
; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
204212
; CHECK-NEXT: frameOffsetReg: '$sgpr33'
205213
; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'

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