Skip to content

Commit 040bb37

Browse files
fhahnfhahn
committed
[VPlan] Fix incorrect argument for CreateBinOp after 06c3a7d.
06c3a7d incorrectly updated CreateBinOp to pass the debug location, which gets interpreted as FPMath node. Remove the argument.
1 parent f664d31 commit 040bb37

File tree

2 files changed

+111
-2
lines changed

2 files changed

+111
-2
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1504,8 +1504,8 @@ void VPWidenIntOrFpInductionRecipe::execute(VPTransformState &State) {
15041504
VecInd->setDebugLoc(EntryVal->getDebugLoc());
15051505
State.set(this, VecInd);
15061506

1507-
Instruction *LastInduction = cast<Instruction>(Builder.CreateBinOp(
1508-
AddOp, VecInd, SplatVF, "vec.ind.next", EntryVal->getDebugLoc()));
1507+
Instruction *LastInduction = cast<Instruction>(
1508+
Builder.CreateBinOp(AddOp, VecInd, SplatVF, "vec.ind.next"));
15091509
if (isa<TruncInst>(EntryVal))
15101510
State.addMetadata(LastInduction, EntryVal);
15111511
LastInduction->setDebugLoc(EntryVal->getDebugLoc());

‎llvm/test/Transforms/LoopVectorize/float-induction.ll‎

Lines changed: 109 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1640,3 +1640,112 @@ for.inc:
16401640
for.end:
16411641
ret void
16421642
}
1643+
1644+
define i32 @float_induction_with_dbg_on_fadd(ptr %dst) {
1645+
; VEC4_INTERL1-LABEL: @float_induction_with_dbg_on_fadd(
1646+
; VEC4_INTERL1-NEXT: entry:
1647+
; VEC4_INTERL1-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
1648+
; VEC4_INTERL1: vector.ph:
1649+
; VEC4_INTERL1-NEXT: br label [[VECTOR_BODY:%.*]]
1650+
; VEC4_INTERL1: vector.body:
1651+
; VEC4_INTERL1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1652+
; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = getelementptr float, ptr null, i64 [[INDEX]]
1653+
; VEC4_INTERL1-NEXT: store <4 x float> poison, ptr [[TMP0]], align 8
1654+
; VEC4_INTERL1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
1655+
; VEC4_INTERL1-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
1656+
; VEC4_INTERL1-NEXT: br i1 [[TMP1]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
1657+
; VEC4_INTERL1: middle.block:
1658+
; VEC4_INTERL1-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
1659+
; VEC4_INTERL1: scalar.ph:
1660+
; VEC4_INTERL1-NEXT: br label [[LOOP:%.*]]
1661+
; VEC4_INTERL1: loop:
1662+
; VEC4_INTERL1-NEXT: br i1 poison, label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
1663+
; VEC4_INTERL1: exit:
1664+
; VEC4_INTERL1-NEXT: ret i32 0
1665+
;
1666+
; VEC4_INTERL2-LABEL: @float_induction_with_dbg_on_fadd(
1667+
; VEC4_INTERL2-NEXT: entry:
1668+
; VEC4_INTERL2-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
1669+
; VEC4_INTERL2: vector.ph:
1670+
; VEC4_INTERL2-NEXT: br label [[VECTOR_BODY:%.*]]
1671+
; VEC4_INTERL2: vector.body:
1672+
; VEC4_INTERL2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1673+
; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = getelementptr float, ptr null, i64 [[INDEX]]
1674+
; VEC4_INTERL2-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i64 16
1675+
; VEC4_INTERL2-NEXT: store <4 x float> poison, ptr [[TMP0]], align 8
1676+
; VEC4_INTERL2-NEXT: store <4 x float> zeroinitializer, ptr [[TMP1]], align 8
1677+
; VEC4_INTERL2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
1678+
; VEC4_INTERL2-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
1679+
; VEC4_INTERL2-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
1680+
; VEC4_INTERL2: middle.block:
1681+
; VEC4_INTERL2-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
1682+
; VEC4_INTERL2: scalar.ph:
1683+
; VEC4_INTERL2-NEXT: br label [[LOOP:%.*]]
1684+
; VEC4_INTERL2: loop:
1685+
; VEC4_INTERL2-NEXT: br i1 poison, label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
1686+
; VEC4_INTERL2: exit:
1687+
; VEC4_INTERL2-NEXT: ret i32 0
1688+
;
1689+
; VEC1_INTERL2-LABEL: @float_induction_with_dbg_on_fadd(
1690+
; VEC1_INTERL2-NEXT: entry:
1691+
; VEC1_INTERL2-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
1692+
; VEC1_INTERL2: vector.ph:
1693+
; VEC1_INTERL2-NEXT: br label [[VECTOR_BODY:%.*]]
1694+
; VEC1_INTERL2: vector.body:
1695+
; VEC1_INTERL2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1696+
; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = or disjoint i64 [[INDEX]], 1
1697+
; VEC1_INTERL2-NEXT: [[TMP1:%.*]] = getelementptr float, ptr null, i64 [[INDEX]]
1698+
; VEC1_INTERL2-NEXT: [[TMP2:%.*]] = getelementptr float, ptr null, i64 [[TMP0]]
1699+
; VEC1_INTERL2-NEXT: store float poison, ptr [[TMP1]], align 8
1700+
; VEC1_INTERL2-NEXT: store float poison, ptr [[TMP2]], align 8
1701+
; VEC1_INTERL2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
1702+
; VEC1_INTERL2-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
1703+
; VEC1_INTERL2-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
1704+
; VEC1_INTERL2: middle.block:
1705+
; VEC1_INTERL2-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
1706+
; VEC1_INTERL2: scalar.ph:
1707+
; VEC1_INTERL2-NEXT: br label [[LOOP:%.*]]
1708+
; VEC1_INTERL2: loop:
1709+
; VEC1_INTERL2-NEXT: br i1 poison, label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP16:![0-9]+]]
1710+
; VEC1_INTERL2: exit:
1711+
; VEC1_INTERL2-NEXT: ret i32 0
1712+
;
1713+
; VEC2_INTERL1_PRED_STORE-LABEL: @float_induction_with_dbg_on_fadd(
1714+
; VEC2_INTERL1_PRED_STORE-NEXT: entry:
1715+
; VEC2_INTERL1_PRED_STORE-NEXT: br label [[VECTOR_BODY:%.*]]
1716+
; VEC2_INTERL1_PRED_STORE: vector.body:
1717+
; VEC2_INTERL1_PRED_STORE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
1718+
; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = getelementptr float, ptr null, i64 [[INDEX]]
1719+
; VEC2_INTERL1_PRED_STORE-NEXT: store <2 x float> poison, ptr [[TMP0]], align 8
1720+
; VEC2_INTERL1_PRED_STORE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
1721+
; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
1722+
; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[TMP1]], label [[EXIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
1723+
; VEC2_INTERL1_PRED_STORE: exit:
1724+
; VEC2_INTERL1_PRED_STORE-NEXT: ret i32 0
1725+
;
1726+
entry:
1727+
br label %loop
1728+
1729+
loop:
1730+
%fp.iv = phi float [ 0.000000e+00, %entry ], [ %fp.iv.next, %loop ], !dbg !4
1731+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
1732+
%fp.iv.next = fadd reassoc float %fp.iv, 0.000000e+00
1733+
%gep = getelementptr float, ptr null, i64 %iv
1734+
store float %fp.iv.next, ptr %gep, align 8
1735+
%iv.next = add i64 %iv, 1
1736+
%exitcond.not = icmp eq i64 %iv.next, 200
1737+
br i1 %exitcond.not, label %exit, label %loop
1738+
1739+
exit:
1740+
ret i32 0
1741+
}
1742+
1743+
!llvm.module.flags = !{!3}
1744+
1745+
!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1)
1746+
!1 = !DIFile(filename: "bbi-99425.c", directory: "/tmp")
1747+
!2 = !{}
1748+
!3 = !{i32 2, !"Debug Info Version", i32 3}
1749+
!4 = !DILocation(line: 5, column: 12, scope: !8)
1750+
!8 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 3, type: !9, unit: !0, retainedNodes: !2)
1751+
!9 = !DISubroutineType(types: !2)

0 commit comments

Comments
 (0)