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[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
1 parent 9a1eded commit 0421049

17 files changed

+82
-21
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ FunctionPass *createSIFoldOperandsLegacyPass();
3939
FunctionPass *createSIPeepholeSDWAPass();
4040
FunctionPass *createSILowerI1CopiesLegacyPass();
4141
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
42-
FunctionPass *createSIShrinkInstructionsPass();
42+
FunctionPass *createSIShrinkInstructionsLegacyPass();
4343
FunctionPass *createSILoadStoreOptimizerLegacyPass();
4444
FunctionPass *createSIWholeQuadModePass();
4545
FunctionPass *createSIFixControlFlowLiveIntervalsPass();
@@ -166,8 +166,8 @@ extern char &SIFoldOperandsLegacyID;
166166
void initializeSIPeepholeSDWAPass(PassRegistry &);
167167
extern char &SIPeepholeSDWAID;
168168

169-
void initializeSIShrinkInstructionsPass(PassRegistry&);
170-
extern char &SIShrinkInstructionsID;
169+
void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
170+
extern char &SIShrinkInstructionsLegacyID;
171171

172172
void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
173173
extern char &SIFixSGPRCopiesLegacyID;

‎llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,4 +100,5 @@ MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
100100
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
101101
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
102102
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
103+
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
103104
#undef MACHINE_FUNCTION_PASS

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939
#include "SILoadStoreOptimizer.h"
4040
#include "SIMachineFunctionInfo.h"
4141
#include "SIMachineScheduler.h"
42+
#include "SIShrinkInstructions.h"
4243
#include "TargetInfo/AMDGPUTargetInfo.h"
4344
#include "Utils/AMDGPUBaseInfo.h"
4445
#include "llvm/Analysis/CGSCCPassManager.h"
@@ -415,7 +416,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
415416
initializeSIFixVGPRCopiesPass(*PR);
416417
initializeSIFoldOperandsLegacyPass(*PR);
417418
initializeSIPeepholeSDWAPass(*PR);
418-
initializeSIShrinkInstructionsPass(*PR);
419+
initializeSIShrinkInstructionsLegacyPass(*PR);
419420
initializeSIOptimizeExecMaskingPreRAPass(*PR);
420421
initializeSIOptimizeVGPRLiveRangePass(*PR);
421422
initializeSILoadStoreOptimizerLegacyPass(*PR);
@@ -1280,7 +1281,7 @@ void GCNPassConfig::addMachineSSAOptimization() {
12801281
addPass(&SIFoldOperandsLegacyID);
12811282
}
12821283
addPass(&DeadMachineInstructionElimID);
1283-
addPass(createSIShrinkInstructionsPass());
1284+
addPass(createSIShrinkInstructionsLegacyPass());
12841285
}
12851286

12861287
bool GCNPassConfig::addILPOpts() {
@@ -1484,7 +1485,7 @@ void GCNPassConfig::addPostRegAlloc() {
14841485

14851486
void GCNPassConfig::addPreSched2() {
14861487
if (TM->getOptLevel() > CodeGenOptLevel::None)
1487-
addPass(createSIShrinkInstructionsPass());
1488+
addPass(createSIShrinkInstructionsLegacyPass());
14881489
addPass(&SIPostRABundlerID);
14891490
}
14901491

‎llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp‎

Lines changed: 37 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
//===----------------------------------------------------------------------===//
99
//
1010

11+
#include "SIShrinkInstructions.h"
1112
#include "AMDGPU.h"
1213
#include "GCNSubtarget.h"
1314
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -26,20 +27,13 @@ using namespace llvm;
2627

2728
namespace {
2829

29-
class SIShrinkInstructions : public MachineFunctionPass {
30+
class SIShrinkInstructions {
3031
MachineFunction *MF;
3132
MachineRegisterInfo *MRI;
3233
const GCNSubtarget *ST;
3334
const SIInstrInfo *TII;
3435
const SIRegisterInfo *TRI;
3536

36-
public:
37-
static char ID;
38-
39-
public:
40-
SIShrinkInstructions() : MachineFunctionPass(ID) {
41-
}
42-
4337
bool foldImmediates(MachineInstr &MI, bool TryToCommute = true) const;
4438
bool shouldShrinkTrue16(MachineInstr &MI) const;
4539
bool isKImmOperand(const MachineOperand &Src) const;
@@ -62,6 +56,18 @@ class SIShrinkInstructions : public MachineFunctionPass {
6256
void dropInstructionKeepingImpDefs(MachineInstr &MI) const;
6357
MachineInstr *matchSwap(MachineInstr &MovT) const;
6458

59+
public:
60+
SIShrinkInstructions() = default;
61+
bool run(MachineFunction &MF);
62+
};
63+
64+
class SIShrinkInstructionsLegacy : public MachineFunctionPass {
65+
66+
public:
67+
static char ID;
68+
69+
SIShrinkInstructionsLegacy() : MachineFunctionPass(ID) {}
70+
6571
bool runOnMachineFunction(MachineFunction &MF) override;
6672

6773
StringRef getPassName() const override { return "SI Shrink Instructions"; }
@@ -74,13 +80,13 @@ class SIShrinkInstructions : public MachineFunctionPass {
7480

7581
} // End anonymous namespace.
7682

77-
INITIALIZE_PASS(SIShrinkInstructions, DEBUG_TYPE,
83+
INITIALIZE_PASS(SIShrinkInstructionsLegacy, DEBUG_TYPE,
7884
"SI Shrink Instructions", false, false)
7985

80-
char SIShrinkInstructions::ID = 0;
86+
char SIShrinkInstructionsLegacy::ID = 0;
8187

82-
FunctionPass *llvm::createSIShrinkInstructionsPass() {
83-
return new SIShrinkInstructions();
88+
FunctionPass *llvm::createSIShrinkInstructionsLegacyPass() {
89+
return new SIShrinkInstructionsLegacy();
8490
}
8591

8692
/// This function checks \p MI for operands defined by a move immediate
@@ -815,9 +821,7 @@ bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
815821
return true;
816822
}
817823

818-
bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
819-
if (skipFunction(MF.getFunction()))
820-
return false;
824+
bool SIShrinkInstructions::run(MachineFunction &MF) {
821825

822826
this->MF = &MF;
823827
MRI = &MF.getRegInfo();
@@ -1077,3 +1081,21 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
10771081
}
10781082
return false;
10791083
}
1084+
1085+
bool SIShrinkInstructionsLegacy::runOnMachineFunction(MachineFunction &MF) {
1086+
if (skipFunction(MF.getFunction()))
1087+
return false;
1088+
1089+
return SIShrinkInstructions().run(MF);
1090+
}
1091+
1092+
PreservedAnalyses
1093+
SIShrinkInstructionsPass::run(MachineFunction &MF,
1094+
MachineFunctionAnalysisManager &) {
1095+
if (MF.getFunction().hasOptNone() || !SIShrinkInstructions().run(MF))
1096+
return PreservedAnalyses::all();
1097+
1098+
auto PA = getMachineFunctionPassPreservedAnalyses();
1099+
PA.preserveSet<CFGAnalyses>();
1100+
return PA;
1101+
}

‎llvm/lib/Target/AMDGPU/SIShrinkInstructions.h‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
//===- SIShrinkInstructions.h -----------------------------------*- C++- *-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
#ifndef LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H
10+
#define LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H
11+
12+
#include "llvm/CodeGen/MachinePassManager.h"
13+
14+
namespace llvm {
15+
16+
class SIShrinkInstructionsPass
17+
: public PassInfoMixin<SIShrinkInstructionsPass> {
18+
public:
19+
SIShrinkInstructionsPass() = default;
20+
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
21+
};
22+
23+
} // namespace llvm
24+
25+
#endif // LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H

‎llvm/test/CodeGen/AMDGPU/cmp_shrink.mir‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
3+
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
34

45
---
56
name: not_shrink_icmp

‎llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
2+
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
23
--- |
34
define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 {
45
%f16.val0 = load volatile half, ptr addrspace(1) undef

‎llvm/test/CodeGen/AMDGPU/fold-multiple.mir‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
2+
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
23
--- |
34
define amdgpu_kernel void @test() #0 {
45
ret void

‎llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
22
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
3+
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
34

45
---
56
name: shrink_kimm32_mov_b32

‎llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -run-pass=si-shrink-instructions %s -o - | FileCheck %s
3+
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -passes=si-shrink-instructions %s -o - | FileCheck %s
34

45
# Make sure flags are preserved when shrinking instructions
56
---

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