Skip to content

Commit 045af21

Browse files
dtcxzywdtcxzyw
committed
[ConstraintElim] Add pre-commit tests. NFC.
1 parent d8b6524 commit 045af21

File tree

1 file changed

+178
-0
lines changed

1 file changed

+178
-0
lines changed

‎llvm/test/Transforms/ConstraintElimination/shr-exact.ll‎

Lines changed: 178 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,178 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
2+
; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s
3+
4+
define i1 @precond_icmp_ashr_and_rhsc(i64 %x) {
5+
; CHECK-LABEL: define i1 @precond_icmp_ashr_and_rhsc(
6+
; CHECK-SAME: i64 [[X:%.*]]) {
7+
; CHECK-NEXT: [[ENTRY:.*:]]
8+
; CHECK-NEXT: [[SHR:%.*]] = ashr exact i64 [[X]], 3
9+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[SHR]], 200
10+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
11+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X]], 9223372036854775800
12+
; CHECK-NEXT: ret i1 [[CMP]]
13+
;
14+
entry:
15+
%shr = ashr exact i64 %x, 3
16+
%cond = icmp ult i64 %shr, 200
17+
call void @llvm.assume(i1 %cond)
18+
%cmp = icmp eq i64 %x, 9223372036854775800
19+
ret i1 %cmp
20+
}
21+
22+
define i1 @precond_icmp_ashr_and_ashr(i64 %x, i64 %y) {
23+
; CHECK-LABEL: define i1 @precond_icmp_ashr_and_ashr(
24+
; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) {
25+
; CHECK-NEXT: [[ENTRY:.*:]]
26+
; CHECK-NEXT: [[SHRX:%.*]] = ashr exact i64 [[X]], 3
27+
; CHECK-NEXT: [[SHRY:%.*]] = ashr exact i64 [[Y]], 3
28+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[SHRX]], [[SHRY]]
29+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
30+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X]], [[Y]]
31+
; CHECK-NEXT: ret i1 [[CMP]]
32+
;
33+
entry:
34+
%shrx = ashr exact i64 %x, 3
35+
%shry = ashr exact i64 %y, 3
36+
%cond = icmp ult i64 %shrx, %shry
37+
call void @llvm.assume(i1 %cond)
38+
%cmp = icmp eq i64 %x, %y
39+
ret i1 %cmp
40+
}
41+
42+
define i1 @precond_icmp_lshr_and_lshr(i64 %x, i64 %y) {
43+
; CHECK-LABEL: define i1 @precond_icmp_lshr_and_lshr(
44+
; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) {
45+
; CHECK-NEXT: [[ENTRY:.*:]]
46+
; CHECK-NEXT: [[SHRX:%.*]] = lshr exact i64 [[X]], 3
47+
; CHECK-NEXT: [[SHRY:%.*]] = lshr exact i64 [[Y]], 3
48+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[SHRX]], [[SHRY]]
49+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
50+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X]], [[Y]]
51+
; CHECK-NEXT: ret i1 [[CMP]]
52+
;
53+
entry:
54+
%shrx = lshr exact i64 %x, 3
55+
%shry = lshr exact i64 %y, 3
56+
%cond = icmp ult i64 %shrx, %shry
57+
call void @llvm.assume(i1 %cond)
58+
%cmp = icmp eq i64 %x, %y
59+
ret i1 %cmp
60+
}
61+
62+
; Negative tests
63+
64+
define i1 @precond_icmp_lshr_and_rhsc_overflow(i8 %x) {
65+
; CHECK-LABEL: define i1 @precond_icmp_lshr_and_rhsc_overflow(
66+
; CHECK-SAME: i8 [[X:%.*]]) {
67+
; CHECK-NEXT: [[ENTRY:.*:]]
68+
; CHECK-NEXT: [[SHR:%.*]] = lshr exact i8 [[X]], 3
69+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i8 [[SHR]], 60
70+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
71+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X]], 8
72+
; CHECK-NEXT: ret i1 [[CMP]]
73+
;
74+
entry:
75+
%shr = lshr exact i8 %x, 3
76+
%cond = icmp ult i8 %shr, 60
77+
call void @llvm.assume(i1 %cond)
78+
%cmp = icmp eq i8 %x, 8
79+
ret i1 %cmp
80+
}
81+
82+
83+
define i1 @precond_icmp_lshr_unknown_shamt_and_rhsc(i8 %x, i8 %shamt) {
84+
; CHECK-LABEL: define i1 @precond_icmp_lshr_unknown_shamt_and_rhsc(
85+
; CHECK-SAME: i8 [[X:%.*]], i8 [[SHAMT:%.*]]) {
86+
; CHECK-NEXT: [[ENTRY:.*:]]
87+
; CHECK-NEXT: [[SHR:%.*]] = lshr exact i8 [[X]], [[SHAMT]]
88+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i8 [[SHR]], 8
89+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
90+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X]], 8
91+
; CHECK-NEXT: ret i1 [[CMP]]
92+
;
93+
entry:
94+
%shr = lshr exact i8 %x, %shamt
95+
%cond = icmp ult i8 %shr, 8
96+
call void @llvm.assume(i1 %cond)
97+
%cmp = icmp eq i8 %x, 8
98+
ret i1 %cmp
99+
}
100+
101+
define i1 @precond_icmp_ashr_and_rhsc_overflow(i8 %x) {
102+
; CHECK-LABEL: define i1 @precond_icmp_ashr_and_rhsc_overflow(
103+
; CHECK-SAME: i8 [[X:%.*]]) {
104+
; CHECK-NEXT: [[ENTRY:.*:]]
105+
; CHECK-NEXT: [[SHR:%.*]] = ashr exact i8 [[X]], 3
106+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i8 [[SHR]], 60
107+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
108+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X]], 8
109+
; CHECK-NEXT: ret i1 [[CMP]]
110+
;
111+
entry:
112+
%shr = ashr exact i8 %x, 3
113+
%cond = icmp ult i8 %shr, 60
114+
call void @llvm.assume(i1 %cond)
115+
%cmp = icmp eq i8 %x, 8
116+
ret i1 %cmp
117+
}
118+
119+
define i1 @precond_icmp_ashr_and_lshr(i64 %x, i64 %y) {
120+
; CHECK-LABEL: define i1 @precond_icmp_ashr_and_lshr(
121+
; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) {
122+
; CHECK-NEXT: [[ENTRY:.*:]]
123+
; CHECK-NEXT: [[SHRX:%.*]] = ashr exact i64 [[X]], 3
124+
; CHECK-NEXT: [[SHRY:%.*]] = lshr exact i64 [[Y]], 3
125+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[SHRX]], [[SHRY]]
126+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
127+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X]], [[Y]]
128+
; CHECK-NEXT: ret i1 [[CMP]]
129+
;
130+
entry:
131+
%shrx = ashr exact i64 %x, 3
132+
%shry = lshr exact i64 %y, 3
133+
%cond = icmp ult i64 %shrx, %shry
134+
call void @llvm.assume(i1 %cond)
135+
%cmp = icmp eq i64 %x, %y
136+
ret i1 %cmp
137+
}
138+
139+
define i1 @precond_icmp_ashr_and_ashr_mismatched_shamt(i64 %x, i64 %y) {
140+
; CHECK-LABEL: define i1 @precond_icmp_ashr_and_ashr_mismatched_shamt(
141+
; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) {
142+
; CHECK-NEXT: [[ENTRY:.*:]]
143+
; CHECK-NEXT: [[SHRX:%.*]] = ashr exact i64 [[X]], 3
144+
; CHECK-NEXT: [[SHRY:%.*]] = ashr exact i64 [[Y]], 4
145+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[SHRX]], [[SHRY]]
146+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
147+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X]], [[Y]]
148+
; CHECK-NEXT: ret i1 [[CMP]]
149+
;
150+
entry:
151+
%shrx = ashr exact i64 %x, 3
152+
%shry = ashr exact i64 %y, 4
153+
%cond = icmp ult i64 %shrx, %shry
154+
call void @llvm.assume(i1 %cond)
155+
%cmp = icmp eq i64 %x, %y
156+
ret i1 %cmp
157+
}
158+
159+
160+
define i1 @precond_icmp_lshr_and_lshr_signed_pred(i64 %x, i64 %y) {
161+
; CHECK-LABEL: define i1 @precond_icmp_lshr_and_lshr_signed_pred(
162+
; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) {
163+
; CHECK-NEXT: [[ENTRY:.*:]]
164+
; CHECK-NEXT: [[SHRX:%.*]] = lshr exact i64 [[X]], 3
165+
; CHECK-NEXT: [[SHRY:%.*]] = lshr exact i64 [[Y]], 3
166+
; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[SHRX]], [[SHRY]]
167+
; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
168+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[X]], [[Y]]
169+
; CHECK-NEXT: ret i1 [[CMP]]
170+
;
171+
entry:
172+
%shrx = lshr exact i64 %x, 3
173+
%shry = lshr exact i64 %y, 3
174+
%cond = icmp slt i64 %shrx, %shry
175+
call void @llvm.assume(i1 %cond)
176+
%cmp = icmp slt i64 %x, %y
177+
ret i1 %cmp
178+
}

0 commit comments

Comments
 (0)