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VOP2 test change for v_sub_rev_f16
1 parent a1d71c3 commit 0460aaf

17 files changed

+570
-342
lines changed

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1820,8 +1820,7 @@ defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx11_gfx12<0x03c>;
18201820

18211821
defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v_add_f16">;
18221822
defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
1823-
defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
1824-
defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
1823+
defm V_SUBREV_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x034, "v_subrev_f16">;
18251824
defm V_MUL_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
18261825
defm V_MUL_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
18271826
defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2.s‎

Lines changed: 45 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2377,50 +2377,65 @@ v_subrev_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
23772377
// W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
23782378
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
23792379

2380-
v_subrev_f16 v5, v1, v2
2381-
// GFX11: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68]
2380+
v_subrev_f16 v5.l, v1.l, v2.l
2381+
// GFX11: v_subrev_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x68]
23822382

2383-
v_subrev_f16 v5, v127, v2
2384-
// GFX11: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68]
2383+
v_subrev_f16 v5.l, v127.l, v2.l
2384+
// GFX11: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68]
23852385

2386-
v_subrev_f16 v5, s1, v2
2387-
// GFX11: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68]
2386+
v_subrev_f16 v5.l, s1, v2.l
2387+
// GFX11: v_subrev_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x68]
23882388

2389-
v_subrev_f16 v5, s105, v2
2390-
// GFX11: v_subrev_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x68]
2389+
v_subrev_f16 v5.l, s105, v2.l
2390+
// GFX11: v_subrev_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x68]
23912391

2392-
v_subrev_f16 v5, vcc_lo, v2
2393-
// GFX11: v_subrev_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x68]
2392+
v_subrev_f16 v5.l, vcc_lo, v2.l
2393+
// GFX11: v_subrev_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x68]
23942394

2395-
v_subrev_f16 v5, vcc_hi, v2
2396-
// GFX11: v_subrev_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x68]
2395+
v_subrev_f16 v5.l, vcc_hi, v2.l
2396+
// GFX11: v_subrev_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x68]
23972397

2398-
v_subrev_f16 v5, ttmp15, v2
2399-
// GFX11: v_subrev_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x68]
2398+
v_subrev_f16 v5.l, ttmp15, v2.l
2399+
// GFX11: v_subrev_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x68]
24002400

2401-
v_subrev_f16 v5, m0, v2
2402-
// GFX11: v_subrev_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x68]
2401+
v_subrev_f16 v5.l, m0, v2.l
2402+
// GFX11: v_subrev_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x68]
24032403

2404-
v_subrev_f16 v5, exec_lo, v2
2405-
// GFX11: v_subrev_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x68]
2404+
v_subrev_f16 v5.l, exec_lo, v2.l
2405+
// GFX11: v_subrev_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x68]
24062406

2407-
v_subrev_f16 v5, exec_hi, v2
2408-
// GFX11: v_subrev_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x68]
2407+
v_subrev_f16 v5.l, exec_hi, v2.l
2408+
// GFX11: v_subrev_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x68]
24092409

2410-
v_subrev_f16 v5, null, v2
2411-
// GFX11: v_subrev_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x68]
2410+
v_subrev_f16 v5.l, null, v2.l
2411+
// GFX11: v_subrev_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x68]
24122412

2413-
v_subrev_f16 v5, -1, v2
2414-
// GFX11: v_subrev_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x68]
2413+
v_subrev_f16 v5.l, -1, v2.l
2414+
// GFX11: v_subrev_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x68]
24152415

2416-
v_subrev_f16 v5, 0.5, v2
2417-
// GFX11: v_subrev_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x68]
2416+
v_subrev_f16 v5.l, 0.5, v2.l
2417+
// GFX11: v_subrev_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x68]
24182418

2419-
v_subrev_f16 v5, src_scc, v2
2420-
// GFX11: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68]
2419+
v_subrev_f16 v5.l, src_scc, v2.l
2420+
// GFX11: v_subrev_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x68]
24212421

2422-
v_subrev_f16 v127, 0xfe0b, v127
2423-
// GFX11: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
2422+
v_subrev_f16 v127.l, 0xfe0b, v127.l
2423+
// GFX11: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
2424+
2425+
v_subrev_f16 v5.l, v1.h, v2.l
2426+
// GFX11: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68]
2427+
2428+
v_subrev_f16 v5.l, v127.h, v2.l
2429+
// GFX11: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68]
2430+
2431+
v_subrev_f16 v127.l, 0.5, v127.l
2432+
// GFX11: v_subrev_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x68]
2433+
2434+
v_subrev_f16 v5.h, src_scc, v2.h
2435+
// GFX11: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69]
2436+
2437+
v_subrev_f16 v127.h, 0xfe0b, v127.h
2438+
// GFX11: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00]
24242439

24252440
v_subrev_f32 v5, v1, v2
24262441
// GFX11: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s‎

Lines changed: 37 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1922,47 +1922,56 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mas
19221922
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
19231923
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
19241924

1925-
v_subrev_f16 v5, v1, v2 quad_perm:[3,2,1,0]
1926-
// GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
1925+
v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
1926+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
19271927

1928-
v_subrev_f16 v5, v1, v2 quad_perm:[0,1,2,3]
1929-
// GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
1928+
v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
1929+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
19301930

1931-
v_subrev_f16 v5, v1, v2 row_mirror
1932-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
1931+
v_subrev_f16 v5.l, v1.l, v2.l row_mirror
1932+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
19331933

1934-
v_subrev_f16 v5, v1, v2 row_half_mirror
1935-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
1934+
v_subrev_f16 v5.l, v1.l, v2.l row_half_mirror
1935+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
19361936

1937-
v_subrev_f16 v5, v1, v2 row_shl:1
1938-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
1937+
v_subrev_f16 v5.l, v1.l, v2.l row_shl:1
1938+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
19391939

1940-
v_subrev_f16 v5, v1, v2 row_shl:15
1941-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
1940+
v_subrev_f16 v5.l, v1.l, v2.l row_shl:15
1941+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
19421942

1943-
v_subrev_f16 v5, v1, v2 row_shr:1
1944-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
1943+
v_subrev_f16 v5.l, v1.l, v2.l row_shr:1
1944+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
19451945

1946-
v_subrev_f16 v5, v1, v2 row_shr:15
1947-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
1946+
v_subrev_f16 v5.l, v1.l, v2.l row_shr:15
1947+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
19481948

1949-
v_subrev_f16 v5, v1, v2 row_ror:1
1950-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
1949+
v_subrev_f16 v5.l, v1.l, v2.l row_ror:1
1950+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
19511951

1952-
v_subrev_f16 v5, v1, v2 row_ror:15
1953-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
1952+
v_subrev_f16 v5.l, v1.l, v2.l row_ror:15
1953+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
19541954

1955-
v_subrev_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1956-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
1955+
v_subrev_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
1956+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
19571957

1958-
v_subrev_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1959-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
1958+
v_subrev_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
1959+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
19601960

1961-
v_subrev_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1962-
// GFX11: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
1961+
v_subrev_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
1962+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
19631963

1964-
v_subrev_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1965-
// GFX11: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
1964+
v_subrev_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
1965+
// GFX11: v_subrev_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
1966+
1967+
v_subrev_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
1968+
// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x5f,0x01,0x01]
1969+
1970+
v_subrev_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1971+
// GFX11: v_subrev_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x69,0x81,0x60,0x09,0x13]
1972+
1973+
v_subrev_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1974+
// GFX11: v_subrev_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x69,0xff,0x6f,0xf5,0x30]
19661975

19671976
v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0]
19681977
// GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s‎

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -427,14 +427,23 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
427427
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
428428
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
429429

430-
v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
431-
// GFX11: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
430+
v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
431+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
432432

433-
v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
434-
// GFX11: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
433+
v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
434+
// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
435435

436-
v_subrev_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
437-
// GFX11: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
436+
v_subrev_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
437+
// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
438+
439+
v_subrev_f16 v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
440+
// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x77,0x39,0x05]
441+
442+
v_subrev_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
443+
// GFX11: v_subrev_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x69,0x81,0x77,0x39,0x05]
444+
445+
v_subrev_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
446+
// GFX11: v_subrev_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x69,0xff,0x00,0x00,0x00]
438447

439448
v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
440449
// GFX11: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s‎

Lines changed: 44 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -308,30 +308,56 @@ v_sub_f16_e32 v5.l, v1.l, v255.l
308308
v_sub_f16_e32 v5.l, v255.l, v2.l
309309
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
310310

311-
v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
312-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
311+
v_subrev_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
312+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
313313

314-
v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
315-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
314+
v_subrev_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
315+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
316316

317-
v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
318-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
317+
v_subrev_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
318+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
319319

320+
v_subrev_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
321+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
320322

321-
v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
322-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
323+
v_subrev_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
324+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
323325

324-
v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
325-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
326+
v_subrev_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
327+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
326328

327-
v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
328-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
329+
v_subrev_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
330+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
329331

330-
v_subrev_f16_e32 v255, v1, v2
331-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
332+
v_subrev_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
333+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
332334

333-
v_subrev_f16_e32 v5, v1, v255
334-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
335+
v_subrev_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
336+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
335337

336-
v_subrev_f16_e32 v5, v255, v2
337-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
338+
v_subrev_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
339+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
340+
341+
v_subrev_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
342+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
343+
344+
v_subrev_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
345+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
346+
347+
v_subrev_f16_e32 v255.h, v1.h, v2.h
348+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
349+
350+
v_subrev_f16_e32 v255.l, v1.l, v2.l
351+
// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
352+
353+
v_subrev_f16_e32 v5.h, v1.h, v255.h
354+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
355+
356+
v_subrev_f16_e32 v5.h, v255.h, v2.h
357+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
358+
359+
v_subrev_f16_e32 v5.l, v1.l, v255.l
360+
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
361+
362+
v_subrev_f16_e32 v5.l, v255.l, v2.l
363+
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction

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