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[RISCV] Add short forward branch support for mul instruction (#166300)
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6 files changed

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6 files changed

+169
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‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -131,6 +131,7 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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case RISCV::PseudoCCMAXU:
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case RISCV::PseudoCCMIN:
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case RISCV::PseudoCCMINU:
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case RISCV::PseudoCCMUL:
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case RISCV::PseudoCCADDW:
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case RISCV::PseudoCCSUBW:
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case RISCV::PseudoCCSLL:
@@ -237,6 +238,7 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
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case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
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case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
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case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
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case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
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case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
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case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
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case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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Original file line numberDiff line numberDiff line change
@@ -1856,6 +1856,11 @@ def TuneShortForwardBranchIMinMax
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"true", "Enable short forward branch optimization for min,max instructions in Zbb",
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[TuneShortForwardBranchOpt]>;
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def TuneShortForwardBranchIMul
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: SubtargetFeature<"short-forward-branch-i-mul", "HasShortForwardBranchIMul",
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"true", "Enable short forward branch optimization for mul instruction",
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[TuneShortForwardBranchOpt]>;
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// Some subtargets require a S2V transfer buffer to move scalars into vectors.
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// FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure.
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def TuneNoSinkSplatOperands

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -1703,6 +1703,7 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
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case RISCV::MAXU: return RISCV::PseudoCCMAXU;
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case RISCV::MIN: return RISCV::PseudoCCMIN;
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case RISCV::MINU: return RISCV::PseudoCCMINU;
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case RISCV::MUL: return RISCV::PseudoCCMUL;
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case RISCV::ADDI: return RISCV::PseudoCCADDI;
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case RISCV::SLLI: return RISCV::PseudoCCSLLI;
@@ -1754,6 +1755,9 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg,
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MI->getOpcode() == RISCV::MINU || MI->getOpcode() == RISCV::MAXU))
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return nullptr;
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if (!STI.hasShortForwardBranchIMul() && MI->getOpcode() == RISCV::MUL)
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return nullptr;
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// Check if MI can be predicated and folded into the CCMOV.
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if (getPredicatedOpcode(MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
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return nullptr;

‎llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,7 @@ def PseudoCCMAX : SFBALU_rr;
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def PseudoCCMIN : SFBALU_rr;
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def PseudoCCMAXU : SFBALU_rr;
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def PseudoCCMINU : SFBALU_rr;
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def PseudoCCMUL : SFBALU_rr;
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def PseudoCCADDI : SFBALU_ri;
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def PseudoCCANDI : SFBALU_ri;

‎llvm/test/CodeGen/RISCV/features-info.ll‎

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Original file line numberDiff line numberDiff line change
@@ -137,6 +137,7 @@
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; CHECK-NEXT: shifted-zextw-fusion - Enable SLLI+SRLI to be fused when computing (shifted) word zero extension.
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; CHECK-NEXT: shlcofideleg - 'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode).
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; CHECK-NEXT: short-forward-branch-i-minmax - Enable short forward branch optimization for min,max instructions in Zbb.
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; CHECK-NEXT: short-forward-branch-i-mul - Enable short forward branch optimization for mul instruction.
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; CHECK-NEXT: short-forward-branch-opt - Enable short forward branch optimization.
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; CHECK-NEXT: shtvala - 'Shtvala' (htval provides all needed values).
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; CHECK-NEXT: shvsatpa - 'Shvsatpa' (vsatp supports all modes supported by satp).

‎llvm/test/CodeGen/RISCV/short-forward-branch-opt-mul.ll‎

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32I-M
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64I-M
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-opt | \
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; RUN: FileCheck %s --check-prefixes=RV32I-SFB-M
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-opt | \
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; RUN: FileCheck %s --check-prefixes=RV64I-SFB-M
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-i-mul | \
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; RUN: FileCheck %s --check-prefixes=RV32I-SFBIMul-M
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-i-mul | \
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; RUN: FileCheck %s --check-prefixes=RV64I-SFBIMul-M
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define i32 @select_example_mul_i32(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
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; RV32I-M-LABEL: select_example_mul_i32:
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; RV32I-M: # %bb.0: # %entry
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; RV32I-M-NEXT: beqz a2, .LBB0_2
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; RV32I-M-NEXT: # %bb.1:
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; RV32I-M-NEXT: mul a1, a0, a3
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; RV32I-M-NEXT: .LBB0_2: # %entry
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; RV32I-M-NEXT: mv a0, a1
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; RV32I-M-NEXT: ret
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;
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; RV64I-M-LABEL: select_example_mul_i32:
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; RV64I-M: # %bb.0: # %entry
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; RV64I-M-NEXT: beqz a2, .LBB0_2
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; RV64I-M-NEXT: # %bb.1:
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; RV64I-M-NEXT: mulw a1, a0, a3
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; RV64I-M-NEXT: .LBB0_2: # %entry
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; RV64I-M-NEXT: mv a0, a1
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; RV64I-M-NEXT: ret
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;
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; RV32I-SFB-M-LABEL: select_example_mul_i32:
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; RV32I-SFB-M: # %bb.0: # %entry
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; RV32I-SFB-M-NEXT: mul a0, a0, a3
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; RV32I-SFB-M-NEXT: bnez a2, .LBB0_2
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; RV32I-SFB-M-NEXT: # %bb.1: # %entry
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; RV32I-SFB-M-NEXT: mv a0, a1
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; RV32I-SFB-M-NEXT: .LBB0_2: # %entry
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; RV32I-SFB-M-NEXT: ret
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;
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; RV64I-SFB-M-LABEL: select_example_mul_i32:
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; RV64I-SFB-M: # %bb.0: # %entry
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; RV64I-SFB-M-NEXT: mulw a0, a0, a3
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; RV64I-SFB-M-NEXT: bnez a2, .LBB0_2
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; RV64I-SFB-M-NEXT: # %bb.1: # %entry
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; RV64I-SFB-M-NEXT: mv a0, a1
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; RV64I-SFB-M-NEXT: .LBB0_2: # %entry
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; RV64I-SFB-M-NEXT: ret
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;
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; RV32I-SFBIMul-M-LABEL: select_example_mul_i32:
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; RV32I-SFBIMul-M: # %bb.0: # %entry
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; RV32I-SFBIMul-M-NEXT: beqz a2, .LBB0_2
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; RV32I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMul-M-NEXT: mul a1, a0, a3
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; RV32I-SFBIMul-M-NEXT: .LBB0_2: # %entry
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; RV32I-SFBIMul-M-NEXT: mv a0, a1
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; RV32I-SFBIMul-M-NEXT: ret
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;
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; RV64I-SFBIMul-M-LABEL: select_example_mul_i32:
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; RV64I-SFBIMul-M: # %bb.0: # %entry
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; RV64I-SFBIMul-M-NEXT: mulw a0, a0, a3
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; RV64I-SFBIMul-M-NEXT: bnez a2, .LBB0_2
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; RV64I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMul-M-NEXT: mv a0, a1
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; RV64I-SFBIMul-M-NEXT: .LBB0_2: # %entry
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; RV64I-SFBIMul-M-NEXT: ret
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entry:
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%res = mul i32 %a, %y
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%sel = select i1 %x, i32 %res, i32 %b
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ret i32 %sel
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}
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define i64 @select_example_mul_i64(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {
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; RV32I-M-LABEL: select_example_mul_i64:
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; RV32I-M: # %bb.0: # %entry
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; RV32I-M-NEXT: beqz a4, .LBB1_2
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; RV32I-M-NEXT: # %bb.1:
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; RV32I-M-NEXT: mul a2, a0, a6
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; RV32I-M-NEXT: mulhu a3, a0, a5
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; RV32I-M-NEXT: mul a1, a1, a5
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; RV32I-M-NEXT: add a2, a3, a2
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; RV32I-M-NEXT: add a3, a2, a1
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; RV32I-M-NEXT: mul a2, a0, a5
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; RV32I-M-NEXT: .LBB1_2: # %entry
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; RV32I-M-NEXT: mv a0, a2
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; RV32I-M-NEXT: mv a1, a3
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; RV32I-M-NEXT: ret
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;
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; RV64I-M-LABEL: select_example_mul_i64:
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; RV64I-M: # %bb.0: # %entry
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; RV64I-M-NEXT: beqz a2, .LBB1_2
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; RV64I-M-NEXT: # %bb.1:
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; RV64I-M-NEXT: mul a1, a0, a3
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; RV64I-M-NEXT: .LBB1_2: # %entry
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; RV64I-M-NEXT: mv a0, a1
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; RV64I-M-NEXT: ret
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;
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; RV32I-SFB-M-LABEL: select_example_mul_i64:
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; RV32I-SFB-M: # %bb.0: # %entry
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; RV32I-SFB-M-NEXT: mul a6, a0, a6
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; RV32I-SFB-M-NEXT: mulhu a7, a0, a5
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; RV32I-SFB-M-NEXT: mul a1, a1, a5
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; RV32I-SFB-M-NEXT: mul a0, a0, a5
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; RV32I-SFB-M-NEXT: add a6, a7, a6
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; RV32I-SFB-M-NEXT: beqz a4, .LBB1_2
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; RV32I-SFB-M-NEXT: # %bb.1: # %entry
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; RV32I-SFB-M-NEXT: add a3, a6, a1
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; RV32I-SFB-M-NEXT: .LBB1_2: # %entry
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; RV32I-SFB-M-NEXT: bnez a4, .LBB1_4
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; RV32I-SFB-M-NEXT: # %bb.3: # %entry
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; RV32I-SFB-M-NEXT: mv a0, a2
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; RV32I-SFB-M-NEXT: .LBB1_4: # %entry
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; RV32I-SFB-M-NEXT: mv a1, a3
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; RV32I-SFB-M-NEXT: ret
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;
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; RV64I-SFB-M-LABEL: select_example_mul_i64:
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; RV64I-SFB-M: # %bb.0: # %entry
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; RV64I-SFB-M-NEXT: mul a0, a0, a3
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; RV64I-SFB-M-NEXT: bnez a2, .LBB1_2
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; RV64I-SFB-M-NEXT: # %bb.1: # %entry
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; RV64I-SFB-M-NEXT: mv a0, a1
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; RV64I-SFB-M-NEXT: .LBB1_2: # %entry
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; RV64I-SFB-M-NEXT: ret
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;
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; RV32I-SFBIMul-M-LABEL: select_example_mul_i64:
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; RV32I-SFBIMul-M: # %bb.0: # %entry
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; RV32I-SFBIMul-M-NEXT: mul a6, a0, a6
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; RV32I-SFBIMul-M-NEXT: mulhu a7, a0, a5
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; RV32I-SFBIMul-M-NEXT: mul a1, a1, a5
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; RV32I-SFBIMul-M-NEXT: add a6, a7, a6
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; RV32I-SFBIMul-M-NEXT: beqz a4, .LBB1_2
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; RV32I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMul-M-NEXT: add a3, a6, a1
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; RV32I-SFBIMul-M-NEXT: .LBB1_2: # %entry
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; RV32I-SFBIMul-M-NEXT: beqz a4, .LBB1_4
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; RV32I-SFBIMul-M-NEXT: # %bb.3: # %entry
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; RV32I-SFBIMul-M-NEXT: mul a2, a0, a5
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; RV32I-SFBIMul-M-NEXT: .LBB1_4: # %entry
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; RV32I-SFBIMul-M-NEXT: mv a0, a2
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; RV32I-SFBIMul-M-NEXT: mv a1, a3
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; RV32I-SFBIMul-M-NEXT: ret
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;
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; RV64I-SFBIMul-M-LABEL: select_example_mul_i64:
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; RV64I-SFBIMul-M: # %bb.0: # %entry
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; RV64I-SFBIMul-M-NEXT: beqz a2, .LBB1_2
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; RV64I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMul-M-NEXT: mul a1, a0, a3
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; RV64I-SFBIMul-M-NEXT: .LBB1_2: # %entry
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; RV64I-SFBIMul-M-NEXT: mv a0, a1
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; RV64I-SFBIMul-M-NEXT: ret
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entry:
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%res = mul i64 %a, %y
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%sel = select i1 %x, i64 %res, i64 %b
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ret i64 %sel
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}
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