Made the following changes

	a)make NOP for Prefetch INST.
	b)updated the testcase.

Author: ukalappa-mips

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -683,9 +683,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (Subtarget.is64Bit())
     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
 
-  if (Subtarget.hasStdExtZicbop() || Subtarget.hasVendorXMIPSCBOP()) {
+  if (Subtarget.hasVendorXMIPSCBOP())
+    setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
+  else if (Subtarget.hasStdExtZicbop())
     setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
-  }
 
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
@@ -6596,6 +6597,17 @@ SDValue RISCVTargetLowering::lowerConstantFP(SDValue Op,
   return DAG.getNode(ISD::FNEG, DL, VT, Const);
 }
 
+static SDValue LowerPREFETCH(SDValue Op, const RISCVSubtarget &Subtarget,
+                             SelectionDAG &DAG) {
+
+  unsigned IsData = Op.getConstantOperandVal(4);
+
+  // mips-p8700  we support data prefetch for now.
+  if (Subtarget.hasVendorXMIPSCBOP() && !IsData)
+    return Op.getOperand(0);
+  return Op;
+}
+
 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   SDLoc dl(Op);
@@ -7164,6 +7176,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   switch (Op.getOpcode()) {
   default:
     report_fatal_error("unimplemented operand");
+  case ISD::PREFETCH:
+    return LowerPREFETCH(Op, Subtarget, DAG);
   case ISD::ATOMIC_FENCE:
     return LowerATOMIC_FENCE(Op, DAG, Subtarget);
   case ISD::GlobalAddress:

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -2766,7 +2766,8 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         CASE_OPERAND_UIMM(6)
         CASE_OPERAND_UIMM(7)
         CASE_OPERAND_UIMM(8)
-        CASE_OPERAND_UIMM(10)
+        CASE_OPERAND_UIMM(9)
+	CASE_OPERAND_UIMM(10)
         CASE_OPERAND_UIMM(12)
         CASE_OPERAND_UIMM(16)
         CASE_OPERAND_UIMM(20)
@@ -2807,9 +2808,6 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         case RISCVOp::OPERAND_UIMM9_LSB000:
           Ok = isShiftedUInt<6, 3>(Imm);
           break;
-        case RISCVOp::OPERAND_UIMM9:
-          Ok = isUInt<9>(Imm);
-          break;
         case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO:
           Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0);
           break;

llvm/test/CodeGen/RISCV/xmips-cbop.ll

@@ -4,13 +4,13 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
 
-define void @prefetch_read(ptr noundef %ptr) nounwind {
-; RV32XMIPSPREFETCH-LABEL: prefetch_read:
+define void @prefetch_data_read(ptr noundef %ptr) nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_data_read:
 ; RV32XMIPSPREFETCH:       # %bb.0: # %entry
 ; RV32XMIPSPREFETCH-NEXT:    mips.pref 8, 1(a0)
 ; RV32XMIPSPREFETCH-NEXT:    ret
 ;
-; RV64XMIPSPREFETCH-LABEL: prefetch_read:
+; RV64XMIPSPREFETCH-LABEL: prefetch_data_read:
 ; RV64XMIPSPREFETCH:       # %bb.0: # %entry
 ; RV64XMIPSPREFETCH-NEXT:    mips.pref 8, 1(a0)
 ; RV64XMIPSPREFETCH-NEXT:    ret
@@ -20,14 +20,14 @@ entry:
   ret void
 }
 
-define void @prefetch_write(ptr noundef %ptr) nounwind  {
-; RV32XMIPSPREFETCH-LABEL: prefetch_write:
+define void @prefetch_data_write(ptr noundef %ptr) nounwind  {
+; RV32XMIPSPREFETCH-LABEL: prefetch_data_write:
 ; RV32XMIPSPREFETCH:       # %bb.0:
 ; RV32XMIPSPREFETCH-NEXT:    addi a0, a0, 512
 ; RV32XMIPSPREFETCH-NEXT:    mips.pref 9, 0(a0)
 ; RV32XMIPSPREFETCH-NEXT:    ret
 ;
-; RV64XMIPSPREFETCH-LABEL: prefetch_write:
+; RV64XMIPSPREFETCH-LABEL: prefetch_data_write:
 ; RV64XMIPSPREFETCH:       # %bb.0:
 ; RV64XMIPSPREFETCH-NEXT:    addi a0, a0, 512
 ; RV64XMIPSPREFETCH-NEXT:    mips.pref 9, 0(a0)
@@ -37,3 +37,15 @@ define void @prefetch_write(ptr noundef %ptr) nounwind  {
   ret void
 }
 
+define void @prefetch_inst_read(ptr noundef %ptr) nounwind  {
+; RV32XMIPSPREFETCH-LABEL: prefetch_inst_read:
+; RV32XMIPSPREFETCH:       # %bb.0:
+; RV32XMIPSPREFETCH-NEXT:    ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_inst_read:
+; RV64XMIPSPREFETCH:       # %bb.0:
+; RV64XMIPSPREFETCH-NEXT:    ret
+  %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 512
+  tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 0)
+  ret void
+}