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Merge branch 'llvm:main' into copy-inout-dev
2 parents 040572f + e861e49 commit 04daa83

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.github/workflows/libcxx-build-and-test.yaml

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ concurrency:
3636
jobs:
3737
stage1:
3838
if: github.repository_owner == 'llvm'
39-
runs-on: llvm-premerge-libcxx-runners
39+
runs-on: llvm-premerge-libcxx-next-runners
4040
continue-on-error: false
4141
strategy:
4242
fail-fast: false
@@ -47,8 +47,8 @@ jobs:
4747
'generic-cxx26',
4848
'generic-modules'
4949
]
50-
cc: [ 'clang-21' ]
51-
cxx: [ 'clang++-21' ]
50+
cc: [ 'clang-22' ]
51+
cxx: [ 'clang++-22' ]
5252
include:
5353
- config: 'generic-gcc'
5454
cc: 'gcc-15'
@@ -73,7 +73,7 @@ jobs:
7373
**/crash_diagnostics/*
7474
stage2:
7575
if: github.repository_owner == 'llvm'
76-
runs-on: llvm-premerge-libcxx-runners
76+
runs-on: llvm-premerge-libcxx-next-runners
7777
needs: [ stage1 ]
7878
continue-on-error: false
7979
strategy:
@@ -86,18 +86,18 @@ jobs:
8686
'generic-cxx20',
8787
'generic-cxx23'
8888
]
89-
cc: [ 'clang-21' ]
90-
cxx: [ 'clang++-21' ]
89+
cc: [ 'clang-22' ]
90+
cxx: [ 'clang++-22' ]
9191
include:
9292
- config: 'generic-gcc-cxx11'
9393
cc: 'gcc-15'
9494
cxx: 'g++-15'
95+
- config: 'generic-cxx26'
96+
cc: 'clang-21'
97+
cxx: 'clang++-21'
9598
- config: 'generic-cxx26'
9699
cc: 'clang-20'
97100
cxx: 'clang++-20'
98-
- config: 'generic-cxx26'
99-
cc: 'clang-19'
100-
cxx: 'clang++-19'
101101
steps:
102102
- uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
103103
- name: ${{ matrix.config }}
@@ -148,27 +148,27 @@ jobs:
148148
'generic-static',
149149
'bootstrapping-build'
150150
]
151-
machine: [ 'llvm-premerge-libcxx-runners' ]
151+
machine: [ 'llvm-premerge-libcxx-next-runners' ]
152152
include:
153153
- config: 'generic-cxx26'
154-
machine: llvm-premerge-libcxx-runners
154+
machine: llvm-premerge-libcxx-next-runners
155155
- config: 'generic-asan'
156-
machine: llvm-premerge-libcxx-runners
156+
machine: llvm-premerge-libcxx-next-runners
157157
- config: 'generic-tsan'
158-
machine: llvm-premerge-libcxx-runners
158+
machine: llvm-premerge-libcxx-next-runners
159159
- config: 'generic-ubsan'
160-
machine: llvm-premerge-libcxx-runners
160+
machine: llvm-premerge-libcxx-next-runners
161161
# Use a larger machine for MSAN to avoid timeout and memory allocation issues.
162162
- config: 'generic-msan'
163-
machine: llvm-premerge-libcxx-runners
163+
machine: llvm-premerge-libcxx-next-runners
164164
runs-on: ${{ matrix.machine }}
165165
steps:
166166
- uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
167167
- name: ${{ matrix.config }}
168168
run: libcxx/utils/ci/run-buildbot ${{ matrix.config }}
169169
env:
170-
CC: clang-21
171-
CXX: clang++-21
170+
CC: clang-22
171+
CXX: clang++-22
172172
- uses: actions/upload-artifact@26f96dfa697d77e81fd5907df203aa23a56210a8 # v4.3.0
173173
if: always()
174174
with:

clang/include/clang/Basic/BuiltinsX86.td

Lines changed: 0 additions & 115 deletions
Original file line numberDiff line numberDiff line change
@@ -945,10 +945,6 @@ let Features = "xop", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in
945945
def vphsubwd : X86Builtin<"_Vector<4, int>(_Vector<8, short>)">;
946946
def vphsubdq : X86Builtin<"_Vector<2, long long int>(_Vector<4, int>)">;
947947
def vpperm : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>, _Vector<16, char>)">;
948-
def vprotb : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">;
949-
def vprotw : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">;
950-
def vprotd : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">;
951-
def vprotq : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int>, _Vector<2, long long int>)">;
952948
def vprotbi : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Constant char)">;
953949
def vprotwi : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Constant char)">;
954950
def vprotdi : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Constant char)">;
@@ -1882,78 +1878,6 @@ let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVect
18821878
def vpshldw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, _Constant int)">;
18831879
}
18841880

1885-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
1886-
def vpshldvd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">;
1887-
}
1888-
1889-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
1890-
def vpshldvd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">;
1891-
}
1892-
1893-
let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
1894-
def vpshldvd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
1895-
}
1896-
1897-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
1898-
def vpshldvq128 : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int>, _Vector<2, long long int>, _Vector<2, long long int>)">;
1899-
}
1900-
1901-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
1902-
def vpshldvq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Vector<4, long long int>)">;
1903-
}
1904-
1905-
let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
1906-
def vpshldvq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Vector<8, long long int>)">;
1907-
}
1908-
1909-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
1910-
def vpshldvw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>, _Vector<8, short>)">;
1911-
}
1912-
1913-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
1914-
def vpshldvw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>, _Vector<16, short>)">;
1915-
}
1916-
1917-
let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
1918-
def vpshldvw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, _Vector<32, short>)">;
1919-
}
1920-
1921-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
1922-
def vpshrdvd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">;
1923-
}
1924-
1925-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
1926-
def vpshrdvd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">;
1927-
}
1928-
1929-
let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
1930-
def vpshrdvd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">;
1931-
}
1932-
1933-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
1934-
def vpshrdvq128 : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int>, _Vector<2, long long int>, _Vector<2, long long int>)">;
1935-
}
1936-
1937-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
1938-
def vpshrdvq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Vector<4, long long int>)">;
1939-
}
1940-
1941-
let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
1942-
def vpshrdvq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Vector<8, long long int>)">;
1943-
}
1944-
1945-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
1946-
def vpshrdvw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>, _Vector<8, short>)">;
1947-
}
1948-
1949-
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
1950-
def vpshrdvw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>, _Vector<16, short>)">;
1951-
}
1952-
1953-
let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
1954-
def vpshrdvw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, _Vector<32, short>)">;
1955-
}
1956-
19571881
let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
19581882
def vpshrdd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Constant int)">;
19591883
}
@@ -2165,28 +2089,10 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256
21652089
}
21662090

21672091
let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
2168-
def prolvd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
2169-
def prolvq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">;
21702092
def prord512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Constant int)">;
21712093
def prorq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Constant int)">;
21722094
}
21732095

2174-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
2175-
def prolvd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">;
2176-
}
2177-
2178-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
2179-
def prolvd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>)">;
2180-
}
2181-
2182-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
2183-
def prolvq128 : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int>, _Vector<2, long long int>)">;
2184-
}
2185-
2186-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
2187-
def prolvq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">;
2188-
}
2189-
21902096
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
21912097
def prord128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Constant int)">;
21922098
}
@@ -2203,27 +2109,6 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256
22032109
def prorq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Constant int)">;
22042110
}
22052111

2206-
let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
2207-
def prorvd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">;
2208-
def prorvq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">;
2209-
}
2210-
2211-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
2212-
def prorvd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">;
2213-
}
2214-
2215-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
2216-
def prorvd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>)">;
2217-
}
2218-
2219-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
2220-
def prorvq128 : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int>, _Vector<2, long long int>)">;
2221-
}
2222-
2223-
let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
2224-
def prorvq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">;
2225-
}
2226-
22272112
let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
22282113
def pshufhw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Constant int)">;
22292114
def pshuflw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Constant int)">;

clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,21 @@ class CIRDataLayout {
3434
void reset(mlir::DataLayoutSpecInterface spec);
3535

3636
bool isBigEndian() const { return bigEndian; }
37+
38+
/// Returns the maximum number of bytes that may be overwritten by
39+
/// storing the specified type.
40+
///
41+
/// If Ty is a scalable vector type, the scalable property will be set and
42+
/// the runtime size will be a positive integer multiple of the base size.
43+
///
44+
/// For example, returns 5 for i36 and 10 for x86_fp80.
45+
llvm::TypeSize getTypeStoreSize(mlir::Type ty) const {
46+
llvm::TypeSize baseSize = getTypeSizeInBits(ty);
47+
return {llvm::divideCeil(baseSize.getKnownMinValue(), 8),
48+
baseSize.isScalable()};
49+
}
50+
51+
llvm::TypeSize getTypeSizeInBits(mlir::Type ty) const;
3752
};
3853

3954
} // namespace cir

clang/include/clang/CIR/MissingFeatures.h

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,6 @@ struct MissingFeatures {
8787
static bool setFunctionAttributes() { return false; }
8888

8989
// CallOp handling
90-
static bool opCallPseudoDtor() { return false; }
9190
static bool opCallAggregateArgs() { return false; }
9291
static bool opCallPaddingArgs() { return false; }
9392
static bool opCallABIExtendArg() { return false; }
@@ -162,6 +161,13 @@ struct MissingFeatures {
162161
static bool addressIsKnownNonNull() { return false; }
163162
static bool addressPointerAuthInfo() { return false; }
164163

164+
// Atomic
165+
static bool atomicExpr() { return false; }
166+
static bool atomicInfo() { return false; }
167+
static bool atomicInfoGetAtomicPointer() { return false; }
168+
static bool atomicInfoGetAtomicAddress() { return false; }
169+
static bool atomicUseLibCall() { return false; }
170+
165171
// Misc
166172
static bool abiArgInfo() { return false; }
167173
static bool addHeapAllocSiteMetadata() { return false; }
@@ -197,7 +203,9 @@ struct MissingFeatures {
197203
static bool ctorMemcpyizer() { return false; }
198204
static bool cudaSupport() { return false; }
199205
static bool cxxRecordStaticMembers() { return false; }
206+
static bool dataLayoutTypeIsSized() { return false; }
200207
static bool dataLayoutTypeAllocSize() { return false; }
208+
static bool dataLayoutTypeStoreSize() { return false; }
201209
static bool deferredCXXGlobalInit() { return false; }
202210
static bool ehCleanupFlags() { return false; }
203211
static bool ehCleanupScope() { return false; }
@@ -238,6 +246,7 @@ struct MissingFeatures {
238246
static bool objCBlocks() { return false; }
239247
static bool objCGC() { return false; }
240248
static bool objCLifetime() { return false; }
249+
static bool openCL() { return false; }
241250
static bool openMP() { return false; }
242251
static bool opTBAA() { return false; }
243252
static bool peepholeProtection() { return false; }

clang/lib/AST/ByteCode/InterpBuiltin.cpp

Lines changed: 21 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1783,11 +1783,24 @@ static bool interp__builtin_memcpy(InterpState &S, CodePtr OpPC,
17831783
if (DestPtr.isDummy() || SrcPtr.isDummy())
17841784
return false;
17851785

1786+
if (DestPtr.getType()->isIncompleteType()) {
1787+
S.FFDiag(S.Current->getSource(OpPC),
1788+
diag::note_constexpr_memcpy_incomplete_type)
1789+
<< Move << DestPtr.getType();
1790+
return false;
1791+
}
1792+
if (SrcPtr.getType()->isIncompleteType()) {
1793+
S.FFDiag(S.Current->getSource(OpPC),
1794+
diag::note_constexpr_memcpy_incomplete_type)
1795+
<< Move << SrcPtr.getType();
1796+
return false;
1797+
}
1798+
17861799
QualType DestElemType = getElemType(DestPtr);
17871800
if (DestElemType->isIncompleteType()) {
17881801
S.FFDiag(S.Current->getSource(OpPC),
1789-
diag::note_constexpr_ltor_incomplete_type)
1790-
<< DestElemType;
1802+
diag::note_constexpr_memcpy_incomplete_type)
1803+
<< Move << DestElemType;
17911804
return false;
17921805
}
17931806

@@ -1832,16 +1845,6 @@ static bool interp__builtin_memcpy(InterpState &S, CodePtr OpPC,
18321845
return false;
18331846
}
18341847

1835-
if (DestElemType->isIncompleteType() ||
1836-
DestPtr.getType()->isIncompleteType()) {
1837-
QualType DiagType =
1838-
DestElemType->isIncompleteType() ? DestElemType : DestPtr.getType();
1839-
S.FFDiag(S.Current->getSource(OpPC),
1840-
diag::note_constexpr_memcpy_incomplete_type)
1841-
<< Move << DiagType;
1842-
return false;
1843-
}
1844-
18451848
if (!DestElemType.isTriviallyCopyableType(ASTCtx)) {
18461849
S.FFDiag(S.Current->getSource(OpPC), diag::note_constexpr_memcpy_nontrivial)
18471850
<< Move << DestElemType;
@@ -2030,8 +2033,13 @@ static bool interp__builtin_memchr(InterpState &S, CodePtr OpPC,
20302033
return true;
20312034
}
20322035

2033-
if (Ptr.isDummy())
2036+
if (Ptr.isDummy()) {
2037+
if (Ptr.getType()->isIncompleteType())
2038+
S.FFDiag(S.Current->getSource(OpPC),
2039+
diag::note_constexpr_ltor_incomplete_type)
2040+
<< Ptr.getType();
20342041
return false;
2042+
}
20352043

20362044
// Null is only okay if the given size is 0.
20372045
if (Ptr.isZero()) {

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