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koachankoachan
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[𝘀𝗽𝗿] initial version
Created using spr 1.3.5
2 parents 5d0e26e + 79ab4d1 commit 055fe7c

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-47
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6 files changed

+68
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‎llvm/lib/Target/Sparc/Sparc.td‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,9 @@ def FeatureVIS2
4949
def FeatureVIS3
5050
: SubtargetFeature<"vis3", "IsVIS3", "true",
5151
"Enable Visual Instruction Set extensions III">;
52+
def FeatureUA2005
53+
: SubtargetFeature<"ua2005", "IsUA2005", "true",
54+
"Enable UltraSPARC Architecture 2005 extensions">;
5255
def FeatureLeon
5356
: SubtargetFeature<"leon", "IsLeon", "true",
5457
"Enable LEON extensions">;
@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
152155
FeatureVIS2],
153156
[TuneSlowRDPC]>;
154157
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
155-
FeatureVIS2]>;
158+
FeatureVIS2, FeatureUA2005]>;
156159
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
157-
FeatureVIS, FeatureVIS2]>;
160+
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
158161
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
159-
FeatureVIS, FeatureVIS2]>;
162+
FeatureVIS, FeatureVIS2, FeatureVIS3,
163+
FeatureUA2005]>;
160164
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
161-
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
165+
FeatureVIS, FeatureVIS2, FeatureVIS3,
166+
FeatureUA2005]>;
162167

163168
// LEON 2 FT generic
164169
def : Processor<"leon2", LEON2Itineraries,

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td‎

Lines changed: 3 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
180180
//===----------------------------------------------------------------------===//
181181

182182
let Predicates = [Is64Bit] in {
183-
184-
def MULXrr : F3_1<2, 0b001001,
185-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
186-
"mulx $rs1, $rs2, $rd",
187-
[(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
188-
def MULXri : F3_2<2, 0b001001,
189-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
190-
"mulx $rs1, $simm13, $rd",
191-
[(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
183+
defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>;
192184

193185
// Division can trap.
194186
let hasSideEffects = 1 in {
195-
def SDIVXrr : F3_1<2, 0b101101,
196-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
197-
"sdivx $rs1, $rs2, $rd",
198-
[(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
199-
def SDIVXri : F3_2<2, 0b101101,
200-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
201-
"sdivx $rs1, $simm13, $rd",
202-
[(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
203-
204-
def UDIVXrr : F3_1<2, 0b001101,
205-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
206-
"udivx $rs1, $rs2, $rd",
207-
[(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
208-
def UDIVXri : F3_2<2, 0b001101,
209-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
210-
"udivx $rs1, $simm13, $rd",
211-
[(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
187+
defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>;
188+
defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>;
212189
} // hasSideEffects = 1
213-
214190
} // Predicates = [Is64Bit]
215191

216192

‎llvm/lib/Target/Sparc/SparcInstrInfo.td‎

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,10 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
4747
def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
4848
AssemblerPredicate<(all_of FeatureVIS3)>;
4949

50+
// HasUA2005 - This is true when the target processor has UA 2005 extensions.
51+
def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
52+
AssemblerPredicate<(all_of FeatureUA2005)>;
53+
5054
// HasHardQuad - This is true when the target processor supports quad floating
5155
// point instructions.
5256
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
@@ -467,22 +471,6 @@ multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
467471
defm A : LoadASI<OpcStr, LoadAOp3Val, RC>;
468472
}
469473

470-
471-
// The LDSTUB instruction is supported for asm only.
472-
// It is unlikely that general-purpose code could make use of it.
473-
// CAS is preferred for sparc v9.
474-
def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
475-
"ldstub [$addr], $rd", []>;
476-
def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
477-
"ldstub [$addr], $rd", []>;
478-
def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
479-
(ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
480-
"ldstuba [$addr] $asi, $rd", []>;
481-
let Predicates = [HasV9], Uses = [ASR3] in
482-
def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
483-
(ins (MEMri $rs1, $simm13):$addr),
484-
"ldstuba [$addr] %asi, $rd", []>;
485-
486474
// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
487475
multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
488476
RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
@@ -740,6 +728,22 @@ let rd = 1, mayStore = 1, Uses = [FSR] in {
740728
"stx %fsr, [$addr]", []>, Requires<[HasV9]>;
741729
}
742730

731+
// B.7. Atomic Load-Store Unsigned Byte Instructions
732+
// (Atomic test-and-set)
733+
// TODO look into the possibility to use this to implment `atomic_flag`.
734+
// If it's possible, then LDSTUB is the preferred way to do it.
735+
def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
736+
"ldstub [$addr], $rd", []>;
737+
def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
738+
"ldstub [$addr], $rd", []>;
739+
def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
740+
(ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
741+
"ldstuba [$addr] $asi, $rd", []>;
742+
let Predicates = [HasV9], Uses = [ASR3] in
743+
def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
744+
(ins (MEMri $rs1, $simm13):$addr),
745+
"ldstuba [$addr] %asi, $rd", []>;
746+
743747
// Section B.8 - SWAP Register with Memory Instruction
744748
// (Atomic swap)
745749
let Constraints = "$val = $rd" in {
@@ -1968,4 +1972,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
19681972

19691973
include "SparcInstr64Bit.td"
19701974
include "SparcInstrVIS.td"
1975+
include "SparcInstrUAOSA.td"
19711976
include "SparcInstrAliases.td"

‎llvm/lib/Target/Sparc/SparcInstrUAOSA.td‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This file contains instruction formats, definitions and patterns needed for
10+
// UA 2005 instructions on SPARC.
11+
//===----------------------------------------------------------------------===//
12+
13+
// UltraSPARC Architecture 2005 Instructions
14+
let Predicates = [HasUA2005] in {
15+
let hasSideEffects = 1 in
16+
def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
17+
let op = 2;
18+
let Inst{29-19} = 0b00010110001;
19+
let Inst{18-0} = 0;
20+
}
21+
} // Predicates = [HasUA2005]

‎llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s
2+
3+
## UA 2005 instructions.
4+
5+
# CHECK: allclean
6+
0x85,0x88,0x00,0x00

‎llvm/test/MC/Sparc/sparc-ua2005.s‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error:
2+
! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005
3+
4+
!! UA 2005 instructions.
5+
6+
! NO-UA2005: error: instruction requires a CPU feature not currently enabled
7+
! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00]
8+
allclean

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