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14 files changed

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14 files changed

+332
-88
lines changed

‎llvm/include/llvm/Target/Target.td‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1154,6 +1154,17 @@ class InstrInfo {
11541154
//
11551155
// This option is a temporary migration help. It will go away.
11561156
bit guessInstructionProperties = true;
1157+
1158+
// Lists of decoder namespaces to coalesce. Each list should consist of one
1159+
// or more names, and the meaning is that each namespace is coalesced with
1160+
// the first namespace in the list. And the order of the namespaces in the
1161+
// list is the attempt order. As an example, if we have
1162+
// [ "", "X", "Y" ]
1163+
// Then namespaces X and Y are coalesced with "", and the decoding is
1164+
// attempted in the order "", then X and then Y.
1165+
// FIXME: Does this need to be done per HWmode, since the decoder tables
1166+
// are generated per HW mode.
1167+
list<list<string>> CoalesceDecoderNamespaces = [[]];
11571168
}
11581169

11591170
// Standard Pseudo Instructions.

‎llvm/lib/Bitcode/Reader/MetadataLoader.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -58,9 +58,6 @@
5858
#include <tuple>
5959
#include <utility>
6060
#include <vector>
61-
namespace llvm {
62-
class Argument;
63-
}
6461

6562
using namespace llvm;
6663

‎llvm/lib/Target/AArch64/AArch64.td‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,10 @@ include "AArch64SchedPredExynos.td"
4040
include "AArch64SchedPredNeoverse.td"
4141
include "AArch64Combine.td"
4242

43-
def AArch64InstrInfo : InstrInfo;
43+
def AArch64InstrInfo : InstrInfo {
44+
// Coalesce "Fallback" and default "" namespaces.
45+
let CoalesceDecoderNamespaces = [["", "Fallback" ]];
46+
}
4447

4548
//===----------------------------------------------------------------------===//
4649
// Named operands for MRS/MSR/TLBI/...

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1608,7 +1608,7 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
16081608
uint32_t Insn =
16091609
(Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
16101610

1611-
const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
1611+
const uint8_t *Tables[] = {DecoderTable32};
16121612

16131613
for (const auto *Table : Tables) {
16141614
DecodeStatus Result =

‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2115,6 +2115,11 @@ def FeatureISAVersion12_Generic: FeatureSet<
21152115

21162116
def AMDGPUInstrInfo : InstrInfo {
21172117
let guessInstructionProperties = 1;
2118+
let CoalesceDecoderNamespaces = [
2119+
["GFX11", "GFX11_FAKE16"],
2120+
["GFX12", "GFX12_FAKE16"],
2121+
["GFX1250", "GFX1250_FAKE16"],
2122+
];
21182123
}
21192124

21202125
def AMDGPUAsmParser : AsmParser {

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 9 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -617,18 +617,15 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
617617
std::bitset<96> DecW = eat12Bytes(Bytes);
618618

619619
if (isGFX11() &&
620-
tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
621-
DecW, Address, CS))
620+
tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS))
622621
break;
623622

624623
if (isGFX1250() &&
625-
tryDecodeInst(DecoderTableGFX125096, DecoderTableGFX1250_FAKE1696, MI,
626-
DecW, Address, CS))
624+
tryDecodeInst(DecoderTableGFX125096, MI, DecW, Address, CS))
627625
break;
628626

629627
if (isGFX12() &&
630-
tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
631-
DecW, Address, CS))
628+
tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS))
632629
break;
633630

634631
if (isGFX12() &&
@@ -698,18 +695,13 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
698695
break;
699696

700697
if (isGFX1250() &&
701-
tryDecodeInst(DecoderTableGFX125064, DecoderTableGFX1250_FAKE1664, MI,
702-
QW, Address, CS))
698+
tryDecodeInst(DecoderTableGFX125064, MI, QW, Address, CS))
703699
break;
704700

705-
if (isGFX12() &&
706-
tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
707-
Address, CS))
701+
if (isGFX12() && tryDecodeInst(DecoderTableGFX1264, MI, QW, Address, CS))
708702
break;
709703

710-
if (isGFX11() &&
711-
tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
712-
Address, CS))
704+
if (isGFX11() && tryDecodeInst(DecoderTableGFX1164, MI, QW, Address, CS))
713705
break;
714706

715707
if (isGFX11() &&
@@ -753,19 +745,14 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
753745
if (isGFX10() && tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS))
754746
break;
755747

756-
if (isGFX11() &&
757-
tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
758-
Address, CS))
748+
if (isGFX11() && tryDecodeInst(DecoderTableGFX1132, MI, DW, Address, CS))
759749
break;
760750

761751
if (isGFX1250() &&
762-
tryDecodeInst(DecoderTableGFX125032, DecoderTableGFX1250_FAKE1632, MI,
763-
DW, Address, CS))
752+
tryDecodeInst(DecoderTableGFX125032, MI, DW, Address, CS))
764753
break;
765754

766-
if (isGFX12() &&
767-
tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
768-
Address, CS))
755+
if (isGFX12() && tryDecodeInst(DecoderTableGFX1232, MI, DW, Address, CS))
769756
break;
770757
}
771758

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -691,9 +691,9 @@ static constexpr DecoderListEntry DecoderList32[]{
691691
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
692692
// Standard Extensions
693693
{DecoderTable32, {}, "standard 32-bit instructions"},
694-
{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
695-
{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
696-
{DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
694+
//{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
695+
//{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
696+
//{DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
697697
};
698698

699699
namespace {
@@ -743,7 +743,7 @@ static constexpr DecoderListEntry DecoderList16[]{
743743
// DecoderTableZicfiss16 must be checked before DecoderTable16.
744744
{DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
745745
{DecoderTable16, {}, "standard 16-bit instructions"},
746-
{DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
746+
//{DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
747747
// Zc* instructions incompatible with Zcf or Zcd
748748
{DecoderTableZcOverlap16,
749749
{},

‎llvm/lib/Target/RISCV/RISCV.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,11 @@ include "RISCVPfmCounters.td"
8585

8686
def RISCVInstrInfo : InstrInfo {
8787
let guessInstructionProperties = 0;
88+
let CoalesceDecoderNamespaces = [
89+
["", "RV32Only", "Zfinx", "ZdinxRV32Only"]
90+
// ["Zicfiss", "", "RV32Only", "ZcOverlap"], // Need to handle RV32Only mappings.
91+
];
92+
8893
}
8994

9095
def RISCVAsmParser : AsmParser {

‎llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,22 +31,22 @@ class I<dag out_ops, dag in_ops> : Instruction {
3131
}
3232

3333
// CHECK: /* 0 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ...
34-
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 0, 15, 0, // Skip to: 22
34+
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 0, 15, 0, // FilterVal = 0x0, Skip to: 22
3535
// CHECK-NEXT: /* 7 */ MCD::OPC_Scope, 8, 0, // Skip to: 18
3636
// CHECK-NEXT: /* 10 */ MCD::OPC_CheckField, 6, 6, 0,
3737
// CHECK-NEXT: /* 14 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
3838
// CHECK-NEXT: /* 18 */ MCD::OPC_TryDecode, 187, 2, 1,
39-
// CHECK-NEXT: /* 22 */ MCD::OPC_FilterValueOrSkip, 1, 15, 0, // Skip to: 41
39+
// CHECK-NEXT: /* 22 */ MCD::OPC_FilterValueOrSkip, 1, 15, 0, // FilterVal = 0x1, Skip to: 41
4040
// CHECK-NEXT: /* 26 */ MCD::OPC_Scope, 8, 0, // Skip to: 37
4141
// CHECK-NEXT: /* 29 */ MCD::OPC_CheckField, 6, 6, 0,
4242
// CHECK-NEXT: /* 33 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
4343
// CHECK-NEXT: /* 37 */ MCD::OPC_TryDecode, 188, 2, 1,
44-
// CHECK-NEXT: /* 41 */ MCD::OPC_FilterValueOrSkip, 2, 15, 0, // Skip to: 60
44+
// CHECK-NEXT: /* 41 */ MCD::OPC_FilterValueOrSkip, 2, 15, 0, // FilterVal = 0x2, Skip to: 60
4545
// CHECK-NEXT: /* 45 */ MCD::OPC_Scope, 8, 0, // Skip to: 56
4646
// CHECK-NEXT: /* 48 */ MCD::OPC_CheckField, 6, 6, 0,
4747
// CHECK-NEXT: /* 52 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
4848
// CHECK-NEXT: /* 56 */ MCD::OPC_TryDecode, 189, 2, 1,
49-
// CHECK-NEXT: /* 60 */ MCD::OPC_FilterValue, 3,
49+
// CHECK-NEXT: /* 60 */ MCD::OPC_FilterValue, 3, // FilterVal = 0x3
5050
// CHECK-NEXT: /* 62 */ MCD::OPC_Scope, 8, 0, // Skip to: 73
5151
// CHECK-NEXT: /* 65 */ MCD::OPC_CheckField, 6, 6, 0,
5252
// CHECK-NEXT: /* 69 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0

‎llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,10 @@ class I : Instruction {
1313
//
1414
// CHECK-LABEL: static const uint8_t DecoderTable128[34] = {
1515
// CHECK-NEXT: /* 0 */ MCD::OPC_ExtractField, 0, 64, // Inst{63-0} ...
16-
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 1, 8, 0, // Skip to: 15
16+
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 1, 8, 0, // FilterVal = 0x1, Skip to: 15
1717
// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 127, 1, 1,
1818
// CHECK-NEXT: /* 11 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I2, DecodeIdx: 0
19-
// CHECK-NEXT: /* 15 */ MCD::OPC_FilterValue, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1,
19+
// CHECK-NEXT: /* 15 */ MCD::OPC_FilterValue, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1, // FilterVal = 0xffffffffffffffff
2020
// CHECK-NEXT: /* 26 */ MCD::OPC_CheckField, 127, 1, 0,
2121
// CHECK-NEXT: /* 30 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I1, DecodeIdx: 0
2222
// CHECK-NEXT: };

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