Skip to content

Commit 0582195

Browse files
arsenmarsenm
committed
AMDGPU: Fold 64-bit immediate into copy to AV class
This is in preparation for patches which will intoduce more copies to av registers.
1 parent 20442f6 commit 0582195

File tree

5 files changed

+70
-82
lines changed

5 files changed

+70
-82
lines changed

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -237,24 +237,24 @@ enum OperandType : unsigned {
237237
OPERAND_REG_INLINE_AC_FP32,
238238
OPERAND_REG_INLINE_AC_FP64,
239239

240+
// Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline
241+
// constants. Does not accept registers.
242+
OPERAND_INLINE_C_AV64_PSEUDO,
243+
240244
// Operand for source modifiers for VOP instructions
241245
OPERAND_INPUT_MODS,
242246

243247
// Operand for SDWA instructions
244248
OPERAND_SDWA_VOPC_DST,
245249

246-
// Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline
247-
// constants.
248-
OPERAND_INLINE_C_AV64_PSEUDO,
249-
250250
OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
251251
OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,
252252

253253
OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
254254
OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,
255255

256256
OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,
257-
OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_FP64,
257+
OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO,
258258

259259
OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
260260
OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,

‎llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1296,7 +1296,8 @@ void SIFoldOperandsImpl::foldOperand(
12961296
for (unsigned MovOp :
12971297
{AMDGPU::S_MOV_B32, AMDGPU::V_MOV_B32_e32, AMDGPU::S_MOV_B64,
12981298
AMDGPU::V_MOV_B64_PSEUDO, AMDGPU::V_MOV_B16_t16_e64,
1299-
AMDGPU::V_ACCVGPR_WRITE_B32_e64, AMDGPU::AV_MOV_B32_IMM_PSEUDO}) {
1299+
AMDGPU::V_ACCVGPR_WRITE_B32_e64, AMDGPU::AV_MOV_B32_IMM_PSEUDO,
1300+
AMDGPU::AV_MOV_B64_IMM_PSEUDO}) {
13001301
const MCInstrDesc &MovDesc = TII->get(MovOp);
13011302
assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1);
13021303

@@ -1312,11 +1313,23 @@ void SIFoldOperandsImpl::foldOperand(
13121313
const int SrcIdx = MovOp == AMDGPU::V_MOV_B16_t16_e64 ? 2 : 1;
13131314
const TargetRegisterClass *MovSrcRC =
13141315
TRI->getRegClass(MovDesc.operands()[SrcIdx].RegClass);
1315-
1316-
if (UseSubReg)
1317-
MovSrcRC = TRI->getMatchingSuperRegClass(SrcRC, MovSrcRC, UseSubReg);
1318-
if (!MRI->constrainRegClass(SrcReg, MovSrcRC))
1319-
break;
1316+
if (MovSrcRC) {
1317+
if (UseSubReg)
1318+
MovSrcRC = TRI->getMatchingSuperRegClass(SrcRC, MovSrcRC, UseSubReg);
1319+
if (!MRI->constrainRegClass(SrcReg, MovSrcRC))
1320+
break;
1321+
1322+
// FIXME: This is mutating the instruction only and deferring the actual
1323+
// fold of the immediate
1324+
} else {
1325+
// For the _IMM_PSEUDO cases, there can be value restrictions on the
1326+
// immediate to verify. Technically we should always verify this, but it
1327+
// only matters for these concrete cases.
1328+
// TODO: Handle non-imm case if it's useful.
1329+
if (!OpToFold.isImm() ||
1330+
!TII->isImmOperandLegal(MovDesc, 1, *OpToFold.getEffectiveImmVal()))
1331+
break;
1332+
}
13201333

13211334
MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
13221335
MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3444,12 +3444,8 @@ bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {
34443444
case AMDGPU::V_ACCVGPR_READ_B32_e64:
34453445
case AMDGPU::V_ACCVGPR_MOV_B32:
34463446
case AMDGPU::AV_MOV_B32_IMM_PSEUDO:
3447-
return true;
34483447
case AMDGPU::AV_MOV_B64_IMM_PSEUDO:
3449-
// TODO: We could fold this, but it's a strange case. The immediate value
3450-
// can't be directly folded into any real use. We would have to spread new
3451-
// immediate legality checks around and only accept subregister extracts for
3452-
// profitability.
3448+
return true;
34533449
default:
34543450
return false;
34553451
}

‎llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir

Lines changed: 34 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,8 @@ tracksRegLiveness: true
77
body: |
88
bb.0:
99
; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_copy_to_areg_64
10-
; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
11-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[V_MOV_B]]
12-
; GCN-NEXT: $agpr0_agpr1 = COPY [[COPY]]
10+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64_align2 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
11+
; GCN-NEXT: $agpr0_agpr1 = COPY [[AV_MOV_]]
1312
; GCN-NEXT: S_ENDPGM 0
1413
%0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
1514
%1:areg_64_align2 = COPY %0
@@ -24,9 +23,8 @@ tracksRegLiveness: true
2423
body: |
2524
bb.0:
2625
; GCN-LABEL: name: v_mov_b64_pseudo_imm_neg1_copy_to_areg_64
27-
; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO -1, implicit $exec
28-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[V_MOV_B]]
29-
; GCN-NEXT: $agpr0_agpr1 = COPY [[COPY]]
26+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64_align2 = AV_MOV_B64_IMM_PSEUDO -1, implicit $exec
27+
; GCN-NEXT: $agpr0_agpr1 = COPY [[AV_MOV_]]
3028
; GCN-NEXT: S_ENDPGM 0
3129
%0:vreg_64_align2 = V_MOV_B64_PSEUDO -1, implicit $exec
3230
%1:areg_64_align2 = COPY %0
@@ -125,9 +123,8 @@ tracksRegLiveness: true
125123
body: |
126124
bb.0:
127125
; GCN-LABEL: name: v_mov_b64_pseudo_imm_0_copy_to_av_64
128-
; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
129-
; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[V_MOV_B]]
130-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
126+
; GCN: [[AV_MOV_:%[0-9]+]]:av_64_align2 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
127+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
131128
%0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
132129
%1:av_64_align2 = COPY %0
133130
S_ENDPGM 0, implicit %1
@@ -226,9 +223,8 @@ tracksRegLiveness: true
226223
body: |
227224
bb.0:
228225
; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_areg_64
229-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec
230-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B64_]]
231-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
226+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
227+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
232228
%0:sreg_64 = S_MOV_B64 0, implicit $exec
233229
%1:areg_64 = COPY %0
234230
S_ENDPGM 0, implicit %1
@@ -241,9 +237,8 @@ tracksRegLiveness: true
241237
body: |
242238
bb.0:
243239
; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_areg_64_align2
244-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec
245-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B64_]]
246-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
240+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64_align2 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
241+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
247242
%0:sreg_64 = S_MOV_B64 0, implicit $exec
248243
%1:areg_64_align2 = COPY %0
249244
S_ENDPGM 0, implicit %1
@@ -256,9 +251,8 @@ tracksRegLiveness: true
256251
body: |
257252
bb.0:
258253
; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_areg_64
259-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec
260-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B64_]]
261-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
254+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64 = AV_MOV_B64_IMM_PSEUDO -16, implicit $exec
255+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
262256
%0:sreg_64 = S_MOV_B64 -16, implicit $exec
263257
%1:areg_64 = COPY %0
264258
S_ENDPGM 0, implicit %1
@@ -271,9 +265,8 @@ tracksRegLiveness: true
271265
body: |
272266
bb.0:
273267
; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_areg_64_align2
274-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec
275-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B64_]]
276-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
268+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64_align2 = AV_MOV_B64_IMM_PSEUDO -16, implicit $exec
269+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
277270
%0:sreg_64 = S_MOV_B64 -16, implicit $exec
278271
%1:areg_64_align2 = COPY %0
279272
S_ENDPGM 0, implicit %1
@@ -286,9 +279,8 @@ tracksRegLiveness: true
286279
body: |
287280
bb.0:
288281
; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_av_64
289-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec
290-
; GCN-NEXT: [[COPY:%[0-9]+]]:av_64 = COPY [[S_MOV_B64_]]
291-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
282+
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
283+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
292284
%0:sreg_64 = S_MOV_B64 0, implicit $exec
293285
%1:av_64 = COPY %0
294286
S_ENDPGM 0, implicit %1
@@ -301,9 +293,8 @@ tracksRegLiveness: true
301293
body: |
302294
bb.0:
303295
; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_av_64_align2
304-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec
305-
; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[S_MOV_B64_]]
306-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
296+
; GCN: [[AV_MOV_:%[0-9]+]]:av_64_align2 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
297+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
307298
%0:sreg_64 = S_MOV_B64 0, implicit $exec
308299
%1:av_64_align2 = COPY %0
309300
S_ENDPGM 0, implicit %1
@@ -316,9 +307,8 @@ tracksRegLiveness: true
316307
body: |
317308
bb.0:
318309
; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_av_64
319-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec
320-
; GCN-NEXT: [[COPY:%[0-9]+]]:av_64 = COPY [[S_MOV_B64_]]
321-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
310+
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO -16, implicit $exec
311+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
322312
%0:sreg_64 = S_MOV_B64 -16, implicit $exec
323313
%1:av_64 = COPY %0
324314
S_ENDPGM 0, implicit %1
@@ -331,9 +321,8 @@ tracksRegLiveness: true
331321
body: |
332322
bb.0:
333323
; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_av_64_align2
334-
; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec
335-
; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[S_MOV_B64_]]
336-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
324+
; GCN: [[AV_MOV_:%[0-9]+]]:av_64_align2 = AV_MOV_B64_IMM_PSEUDO -16, implicit $exec
325+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
337326
%0:sreg_64 = S_MOV_B64 -16, implicit $exec
338327
%1:av_64_align2 = COPY %0
339328
S_ENDPGM 0, implicit %1
@@ -346,9 +335,8 @@ tracksRegLiveness: true
346335
body: |
347336
bb.0:
348337
; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_areg_64
349-
; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
350-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B]]
351-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
338+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64 = AV_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
339+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
352340
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec
353341
%1:areg_64 = COPY %0
354342
S_ENDPGM 0, implicit %1
@@ -361,9 +349,8 @@ tracksRegLiveness: true
361349
body: |
362350
bb.0:
363351
; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_areg_64_align2
364-
; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
365-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B]]
366-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
352+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64_align2 = AV_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
353+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
367354
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec
368355
%1:areg_64_align2 = COPY %0
369356
S_ENDPGM 0, implicit %1
@@ -376,9 +363,8 @@ tracksRegLiveness: true
376363
body: |
377364
bb.0:
378365
; GCN-LABEL: name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_areg_64
379-
; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -21474836480, implicit $exec
380-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B]]
381-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
366+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64 = AV_MOV_B64_IMM_PSEUDO -21474836480, implicit $exec
367+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
382368
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744052234715136, implicit $exec
383369
%1:areg_64 = COPY %0
384370
S_ENDPGM 0, implicit %1
@@ -391,9 +377,8 @@ tracksRegLiveness: true
391377
body: |
392378
bb.0:
393379
; GCN-LABEL: name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_areg_64_align2
394-
; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -21474836480, implicit $exec
395-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B]]
396-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
380+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64_align2 = AV_MOV_B64_IMM_PSEUDO -21474836480, implicit $exec
381+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
397382
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744052234715136, implicit $exec
398383
%1:areg_64_align2 = COPY %0
399384
S_ENDPGM 0, implicit %1
@@ -406,9 +391,8 @@ tracksRegLiveness: true
406391
body: |
407392
bb.0:
408393
; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_av_64
409-
; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
410-
; GCN-NEXT: [[COPY:%[0-9]+]]:av_64 = COPY [[S_MOV_B]]
411-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
394+
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
395+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
412396
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec
413397
%1:av_64 = COPY %0
414398
S_ENDPGM 0, implicit %1
@@ -421,9 +405,8 @@ tracksRegLiveness: true
421405
body: |
422406
bb.0:
423407
; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_av_64_align2
424-
; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
425-
; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[S_MOV_B]]
426-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
408+
; GCN: [[AV_MOV_:%[0-9]+]]:av_64_align2 = AV_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec
409+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
427410
%0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec
428411
%1:av_64_align2 = COPY %0
429412
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -816,9 +816,8 @@ tracksRegLiveness: true
816816
body: |
817817
bb.0:
818818
; GCN-LABEL: name: av_mov_b64_imm_pseudo_copy_av_64_to_virtreg_agpr
819-
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
820-
; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[AV_MOV_]]
821-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
819+
; GCN: [[AV_MOV_:%[0-9]+]]:areg_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
820+
; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]
822821
%0:av_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
823822
%1:areg_64 = COPY %0
824823
S_ENDPGM 0, implicit %1
@@ -832,9 +831,8 @@ tracksRegLiveness: true
832831
body: |
833832
bb.0:
834833
; GCN-LABEL: name: av_mov_b64_imm_pseudo_copy_av_64_to_virtreg_vgpr_0
835-
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
836-
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY [[AV_MOV_]]
837-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
834+
; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec
835+
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B]]
838836
%0:av_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec
839837
%1:vreg_64 = COPY %0
840838
S_ENDPGM 0, implicit %1
@@ -848,9 +846,9 @@ tracksRegLiveness: true
848846
body: |
849847
bb.0:
850848
; GCN-LABEL: name: av_mov_b64_imm_pseudo_copy_av_64_to_virtreg_vgpr_nonsplat_value
851-
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO 274877906961, implicit $exec
852-
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY [[AV_MOV_]]
853-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
849+
; GCN: [[AV_MOV_:%[0-9]+]]:vreg_64 = AV_MOV_B64_IMM_PSEUDO 274877906961, implicit $exec
850+
; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO [[AV_MOV_]], implicit $exec
851+
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B]]
854852
%0:av_64 = AV_MOV_B64_IMM_PSEUDO 274877906961, implicit $exec
855853
%1:vreg_64 = COPY %0
856854
S_ENDPGM 0, implicit %1
@@ -863,9 +861,8 @@ tracksRegLiveness: true
863861
body: |
864862
bb.0:
865863
; GCN-LABEL: name: av_mov_b64_imm_pseudo_copy_av_64_to_virtreg_vgpr_nonsplat_value_copy_sub0
866-
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO 274877906961, implicit $exec
867-
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[AV_MOV_]].sub0
868-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
864+
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 17, implicit $exec
865+
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
869866
%0:av_64 = AV_MOV_B64_IMM_PSEUDO 274877906961, implicit $exec
870867
%1:vgpr_32 = COPY %0.sub0
871868
S_ENDPGM 0, implicit %1
@@ -878,9 +875,8 @@ tracksRegLiveness: true
878875
body: |
879876
bb.0:
880877
; GCN-LABEL: name: av_mov_b64_imm_pseudo_copy_av_64_to_virtreg_vgpr_nonsplat_value_copy_sub1
881-
; GCN: [[AV_MOV_:%[0-9]+]]:av_64 = AV_MOV_B64_IMM_PSEUDO 274877906961, implicit $exec
882-
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[AV_MOV_]].sub1
883-
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]]
878+
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 64, implicit $exec
879+
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
884880
%0:av_64 = AV_MOV_B64_IMM_PSEUDO 274877906961, implicit $exec
885881
%1:vgpr_32 = COPY %0.sub1
886882
S_ENDPGM 0, implicit %1

0 commit comments

Comments
 (0)