Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.

This reverts commit 9cc8442.
This reverts commit 859c871.

A performance regression was reported on the original review.  There appears
to have been an unexpected interaction here.  Reverting during investigation.

Author: preames

llvm/lib/Target/RISCV/RISCV.td

@@ -46,7 +46,6 @@ include "RISCVMacroFusion.td"
 // RISC-V Scheduling Models
 //===----------------------------------------------------------------------===//
 
-include "RISCVSchedGeneric.td"
 include "RISCVSchedMIPSP8700.td"
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -89,20 +89,20 @@ class RISCVTuneProcessorModel<string n,
 defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
 
 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
-                                       GenericModel,
+                                       NoSchedModel,
                                        [Feature32Bit,
                                         FeatureStdExtI],
                                        GenericTuneFeatures>,
                    GenericTuneInfo;
 def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
-                                       GenericModel,
+                                       NoSchedModel,
                                        [Feature64Bit,
                                         FeatureStdExtI],
                                        GenericTuneFeatures>,
                    GenericTuneInfo;
 // Support generic for compatibility with other targets. The triple will be used
 // to change to the appropriate rv32/rv64 version.
-def GENERIC : RISCVTuneProcessorModel<"generic", GenericModel>, GenericTuneInfo;
+def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
 
 def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
                                      MIPSP8700Model,
@@ -496,7 +496,7 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
                                                   TunePostRAScheduler]>;
 
 def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
-                                            GenericModel,
+                                            NoSchedModel,
                                             [Feature64Bit,
                                              FeatureStdExtI,
                                              FeatureStdExtZifencei,
@@ -556,7 +556,7 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneShiftedZExtWFusion]>;
 
 def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
-                                       GenericModel,
+                                       NoSchedModel,
                                        !listconcat(RVA22S64Features,
                                        [FeatureStdExtV,
                                         FeatureStdExtSscofpmf,
@@ -581,7 +581,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
 }
 
 def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
-                                         GenericModel,
+                                         NoSchedModel,
                                          [Feature32Bit,
                                           FeatureStdExtI,
                                           FeatureStdExtM,

llvm/lib/Target/RISCV/RISCVSchedGeneric.td

@@ -212,30 +212,30 @@ define i64 @add64_accept(i64 %a) nounwind {
 define void @add32_reject() nounwind {
 ; RV32I-LABEL: add32_reject:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    lui a1, %hi(ga)
-; RV32I-NEXT:    lui a2, %hi(gb)
-; RV32I-NEXT:    lw a3, %lo(ga)(a1)
-; RV32I-NEXT:    lw a4, %lo(gb)(a2)
-; RV32I-NEXT:    addi a0, a0, -1096
-; RV32I-NEXT:    add a3, a3, a0
-; RV32I-NEXT:    add a0, a4, a0
-; RV32I-NEXT:    sw a3, %lo(ga)(a1)
-; RV32I-NEXT:    sw a0, %lo(gb)(a2)
+; RV32I-NEXT:    lui a0, %hi(ga)
+; RV32I-NEXT:    lui a1, %hi(gb)
+; RV32I-NEXT:    lw a2, %lo(ga)(a0)
+; RV32I-NEXT:    lw a3, %lo(gb)(a1)
+; RV32I-NEXT:    lui a4, 1
+; RV32I-NEXT:    addi a4, a4, -1096
+; RV32I-NEXT:    add a2, a2, a4
+; RV32I-NEXT:    add a3, a3, a4
+; RV32I-NEXT:    sw a2, %lo(ga)(a0)
+; RV32I-NEXT:    sw a3, %lo(gb)(a1)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add32_reject:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    lui a1, %hi(ga)
-; RV64I-NEXT:    lui a2, %hi(gb)
-; RV64I-NEXT:    lw a3, %lo(ga)(a1)
-; RV64I-NEXT:    lw a4, %lo(gb)(a2)
-; RV64I-NEXT:    addi a0, a0, -1096
-; RV64I-NEXT:    add a3, a3, a0
-; RV64I-NEXT:    add a0, a4, a0
-; RV64I-NEXT:    sw a3, %lo(ga)(a1)
-; RV64I-NEXT:    sw a0, %lo(gb)(a2)
+; RV64I-NEXT:    lui a0, %hi(ga)
+; RV64I-NEXT:    lui a1, %hi(gb)
+; RV64I-NEXT:    lw a2, %lo(ga)(a0)
+; RV64I-NEXT:    lw a3, %lo(gb)(a1)
+; RV64I-NEXT:    lui a4, 1
+; RV64I-NEXT:    addi a4, a4, -1096
+; RV64I-NEXT:    add a2, a2, a4
+; RV64I-NEXT:    add a3, a3, a4
+; RV64I-NEXT:    sw a2, %lo(ga)(a0)
+; RV64I-NEXT:    sw a3, %lo(gb)(a1)
 ; RV64I-NEXT:    ret
   %1 = load i32, ptr @ga, align 4
   %2 = load i32, ptr @gb, align 4