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1 parent 4779488 commit 059e49cCopy full SHA for 059e49c
llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -24,7 +24,7 @@ let SchedModel = Andes45Model in {
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//===----------------------------------------------------------------------===//
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// Andes 45 series CPU
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-// - 2 Interger Arithmetic and Logical Units (ALU)
+// - 2 Integer Arithmetic and Logical Units (ALU)
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// - Multiply / Divide Unit (MDU)
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// - Load Store Unit (LSU)
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// - Control and Status Register Unit (CSR)
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