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arsenmarsenm
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AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass (#155125)
This function is used to implement TargetInstrInfo::getRegClass and conceptually should not depend on the dynamic state of the function.
1 parent 0eebb8b commit 05f208a

23 files changed

+237
-235
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5942,7 +5942,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI,
59425942
const MachineRegisterInfo &MRI,
59435943
const MCInstrDesc &TID, unsigned RCID,
59445944
bool IsAllocatable) {
5945-
if ((IsAllocatable || !ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) &&
5945+
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
59465946
(((TID.mayLoad() || TID.mayStore()) &&
59475947
!(TID.TSFlags & SIInstrFlags::Spill)) ||
59485948
(TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) {

‎llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,9 @@ define void @uniform_br_no_metadata(i32 noundef inreg %value, ptr addrspace(8) n
1414
; GFX9-NEXT: s_mov_b32 s6, s19
1515
; GFX9-NEXT: s_mov_b32 s5, s18
1616
; GFX9-NEXT: s_mov_b32 s4, s17
17-
; GFX9-NEXT: v_mov_b32_e32 v0, s16
18-
; GFX9-NEXT: v_mov_b32_e32 v1, s21
19-
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
17+
; GFX9-NEXT: v_mov_b32_e32 v1, s16
18+
; GFX9-NEXT: v_mov_b32_e32 v0, s21
19+
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
2020
; GFX9-NEXT: .LBB0_2: ; %if.end
2121
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2222
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -61,9 +61,9 @@ define void @uniform_br_same_weight(i32 noundef inreg %value, ptr addrspace(8) n
6161
; GFX9-NEXT: s_mov_b32 s6, s19
6262
; GFX9-NEXT: s_mov_b32 s5, s18
6363
; GFX9-NEXT: s_mov_b32 s4, s17
64-
; GFX9-NEXT: v_mov_b32_e32 v0, s16
65-
; GFX9-NEXT: v_mov_b32_e32 v1, s21
66-
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
64+
; GFX9-NEXT: v_mov_b32_e32 v1, s16
65+
; GFX9-NEXT: v_mov_b32_e32 v0, s21
66+
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
6767
; GFX9-NEXT: .LBB1_2: ; %if.end
6868
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6969
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -108,9 +108,9 @@ define void @uniform_br_then_likely(i32 noundef inreg %value, ptr addrspace(8) n
108108
; GFX9-NEXT: s_mov_b32 s6, s19
109109
; GFX9-NEXT: s_mov_b32 s5, s18
110110
; GFX9-NEXT: s_mov_b32 s4, s17
111-
; GFX9-NEXT: v_mov_b32_e32 v0, s16
112-
; GFX9-NEXT: v_mov_b32_e32 v1, s21
113-
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
111+
; GFX9-NEXT: v_mov_b32_e32 v1, s16
112+
; GFX9-NEXT: v_mov_b32_e32 v0, s21
113+
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
114114
; GFX9-NEXT: .LBB2_2: ; %if.end
115115
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
116116
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -156,9 +156,9 @@ define void @divergent_br_no_metadata(i32 noundef inreg %value, ptr addrspace(8)
156156
; GFX9-NEXT: s_mov_b32 s6, s19
157157
; GFX9-NEXT: s_mov_b32 s5, s18
158158
; GFX9-NEXT: s_mov_b32 s4, s17
159-
; GFX9-NEXT: v_mov_b32_e32 v0, s16
160-
; GFX9-NEXT: v_mov_b32_e32 v1, s21
161-
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
159+
; GFX9-NEXT: v_mov_b32_e32 v1, s16
160+
; GFX9-NEXT: v_mov_b32_e32 v0, s21
161+
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
162162
; GFX9-NEXT: .LBB3_2: ; %if.end
163163
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
164164
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -227,9 +227,9 @@ define void @divergent_br_same_weight(i32 noundef inreg %value, ptr addrspace(8)
227227
; GFX9-NEXT: s_mov_b32 s6, s19
228228
; GFX9-NEXT: s_mov_b32 s5, s18
229229
; GFX9-NEXT: s_mov_b32 s4, s17
230-
; GFX9-NEXT: v_mov_b32_e32 v0, s16
231-
; GFX9-NEXT: v_mov_b32_e32 v1, s21
232-
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
230+
; GFX9-NEXT: v_mov_b32_e32 v1, s16
231+
; GFX9-NEXT: v_mov_b32_e32 v0, s21
232+
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
233233
; GFX9-NEXT: .LBB4_2: ; %if.end
234234
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
235235
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -297,9 +297,9 @@ define void @divergent_br_then_likely(i32 noundef inreg %value, ptr addrspace(8)
297297
; GFX9-NEXT: s_mov_b32 s6, s19
298298
; GFX9-NEXT: s_mov_b32 s5, s18
299299
; GFX9-NEXT: s_mov_b32 s4, s17
300-
; GFX9-NEXT: v_mov_b32_e32 v0, s16
301-
; GFX9-NEXT: v_mov_b32_e32 v1, s21
302-
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
300+
; GFX9-NEXT: v_mov_b32_e32 v1, s16
301+
; GFX9-NEXT: v_mov_b32_e32 v0, s21
302+
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
303303
; GFX9-NEXT: ; %bb.2: ; %if.end
304304
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
305305
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

‎llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -166,13 +166,14 @@ define amdgpu_kernel void @with_private_to_flat_addrspacecast_cc_kernel(ptr addr
166166
; GFX942-ARCH-FLAT: ; %bb.0:
167167
; GFX942-ARCH-FLAT-NEXT: s_load_dword s2, s[4:5], 0x0
168168
; GFX942-ARCH-FLAT-NEXT: s_mov_b64 s[0:1], src_private_base
169-
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v2, 0
169+
; GFX942-ARCH-FLAT-NEXT: s_mov_b32 s0, 0
170+
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v2, s0
170171
; GFX942-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
171172
; GFX942-ARCH-FLAT-NEXT: s_cmp_lg_u32 s2, -1
172-
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s0, s1, 0
173-
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s1, s2, 0
174-
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v0, s1
175-
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v1, s0
173+
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s1, s1, 0
174+
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s2, s2, 0
175+
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v0, s2
176+
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v1, s1
176177
; GFX942-ARCH-FLAT-NEXT: flat_store_dword v[0:1], v2 sc0 sc1
177178
; GFX942-ARCH-FLAT-NEXT: s_waitcnt vmcnt(0)
178179
; GFX942-ARCH-FLAT-NEXT: s_endpgm

‎llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
88
; CHECK-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x0
99
; CHECK-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
1010
; CHECK-NEXT: v_mov_b32_e32 v1, 0x3e21eeb6
11-
; CHECK-NEXT: v_mov_b32_e32 v2, 0xa17f65f6
11+
; CHECK-NEXT: v_mov_b32_e32 v20, 0
1212
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
1313
; CHECK-NEXT: s_bitcmp1_b32 s0, 0
1414
; CHECK-NEXT: s_cselect_b64 s[16:17], -1, 0
@@ -22,6 +22,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
2222
; CHECK-NEXT: s_xor_b64 s[20:21], s[2:3], -1
2323
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
2424
; CHECK-NEXT: v_accvgpr_write_b32 a2, v0
25+
; CHECK-NEXT: v_mov_b32_e32 v2, 0xa17f65f6
2526
; CHECK-NEXT: v_mov_b32_e32 v3, 0xbe927e4f
2627
; CHECK-NEXT: v_mov_b32_e32 v4, 0x19f4ec90
2728
; CHECK-NEXT: v_mov_b32_e32 v5, 0x3efa01a0
@@ -42,7 +43,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
4243
; CHECK-NEXT: v_mov_b32_e32 v18, 0x55555523
4344
; CHECK-NEXT: v_mov_b32_e32 v19, 0xbfd55555
4445
; CHECK-NEXT: s_and_b64 s[6:7], exec, s[18:19]
45-
; CHECK-NEXT: v_mov_b32_e32 v20, 0
46+
; CHECK-NEXT: v_mov_b32_e32 v21, v20
4647
; CHECK-NEXT: ; implicit-def: $vgpr30_vgpr31
4748
; CHECK-NEXT: ; implicit-def: $vgpr22_vgpr23
4849
; CHECK-NEXT: s_branch .LBB0_2
@@ -155,7 +156,6 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
155156
; CHECK-NEXT: s_cbranch_vccz .LBB0_1
156157
; CHECK-NEXT: ; %bb.16: ; %._crit_edge2105.i.i.i2330
157158
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
158-
; CHECK-NEXT: v_mov_b32_e32 v21, v20
159159
; CHECK-NEXT: s_mov_b64 s[24:25], 0
160160
; CHECK-NEXT: global_store_dwordx2 v20, v[20:21], s[12:13]
161161
; CHECK-NEXT: s_branch .LBB0_1

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