Skip to content

Commit 0613d36

Browse files
committed
[X86] Refactor whitespace in LowerFABSorFNEG for improved readability (format)
1 parent dca9106 commit 0613d36

File tree

1 file changed

+4
-5
lines changed

1 file changed

+4
-5
lines changed

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22288,8 +22288,7 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
2228822288

2228922289
bool IsFABS = (Op.getOpcode() == ISD::FABS);
2229022290
SDLoc dl(Op);
22291-
MVT VT
22292-
= Op.getSimpleValueType();
22291+
MVT VT = Op.getSimpleValueType();
2229322292

2229422293
// Handle scalar _Float16 (f16) directly via integer bitwise operations.
2229522294
if (VT == MVT::f16) {
@@ -22306,13 +22305,13 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
2230622305
APInt MaskVal;
2230722306
unsigned LogicOp;
2230822307
if (IsFABS) {
22309-
MaskVal = APInt(16, 0x7FFF); // Clear sign bit.
22308+
MaskVal = APInt(16, 0x7FFF); // Clear sign bit.
2231022309
LogicOp = ISD::AND;
2231122310
} else if (IsFNABS) {
22312-
MaskVal = APInt(16, 0x8000); // Combine masks via OR.
22311+
MaskVal = APInt(16, 0x8000); // Combine masks via OR.
2231322312
LogicOp = ISD::OR;
2231422313
} else {
22315-
MaskVal = APInt(16, 0x8000); // Flip sign bit.
22314+
MaskVal = APInt(16, 0x8000); // Flip sign bit.
2231622315
LogicOp = ISD::XOR;
2231722316
}
2231822317

0 commit comments

Comments
 (0)