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[RISCV] Add MC support for more P extension instructions.
This implements pages 10-14 from https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Test cases copied from #123271 with a couple mistakes fixed. Co-authored-by: realqhc <[email protected]>
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‎llvm/lib/Target/RISCV/RISCVInstrInfoP.td‎

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Original file line numberDiff line numberDiff line change
@@ -149,6 +149,15 @@ class RVPBinaryScalar_rr<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr>
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let Inst{26-25} = w;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class RVPBinary_rr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
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: RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
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let Inst{31} = 0b1;
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let Inst{30-27} = f;
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let Inst{26-25} = w;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
@@ -292,3 +301,250 @@ let Predicates = [HasStdExtP, IsRV64] in {
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def PSRA_WS : RVPBinaryScalar_rr<0b100, 0b01, 0b100, "psra.ws">;
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} // Predicates = [HasStdExtP, IsRV64]
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let Predicates = [HasStdExtP] in {
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def PADD_H : RVPBinary_rr<0b0000, 0b00, 0b000, "padd.h">;
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def PADD_B : RVPBinary_rr<0b0000, 0b10, 0b000, "padd.b">;
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def PSADD_H : RVPBinary_rr<0b0010, 0b00, 0b000, "psadd.h">;
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def PSADD_B : RVPBinary_rr<0b0010, 0b10, 0b000, "psadd.b">;
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def PAADD_H : RVPBinary_rr<0b0011, 0b00, 0b000, "paadd.h">;
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def PAADD_B : RVPBinary_rr<0b0011, 0b10, 0b000, "paadd.b">;
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def PSADDU_H : RVPBinary_rr<0b0110, 0b00, 0b000, "psaddu.h">;
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def PSADDU_B : RVPBinary_rr<0b0110, 0b10, 0b000, "psaddu.b">;
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def PAADDU_H : RVPBinary_rr<0b0111, 0b00, 0b000, "paaddu.h">;
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def PAADDU_B : RVPBinary_rr<0b0111, 0b10, 0b000, "paaddu.b">;
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def PSUB_H : RVPBinary_rr<0b1000, 0b00, 0b000, "psub.h">;
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def PSUB_B : RVPBinary_rr<0b1000, 0b10, 0b000, "psub.b">;
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def PDIF_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pdif.h">;
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def PDIF_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pdif.b">;
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def PSSUB_H : RVPBinary_rr<0b1010, 0b00, 0b000, "pssub.h">;
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def PSSUB_B : RVPBinary_rr<0b1010, 0b10, 0b000, "pssub.b">;
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def PASUB_H : RVPBinary_rr<0b1011, 0b00, 0b000, "pasub.h">;
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def PASUB_B : RVPBinary_rr<0b1011, 0b10, 0b000, "pasub.b">;
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def PDIFU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pdifu.h">;
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def PDIFU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pdifu.b">;
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def PSSUBU_H : RVPBinary_rr<0b1110, 0b00, 0b000, "pssubu.h">;
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def PSSUBU_B : RVPBinary_rr<0b1110, 0b10, 0b000, "pssubu.b">;
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def PASUBU_H : RVPBinary_rr<0b1111, 0b00, 0b000, "pasubu.h">;
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def PASUBU_B : RVPBinary_rr<0b1111, 0b10, 0b000, "pasubu.b">;
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} // Predicates = [HasStdExtP]
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let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
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def SADD : RVPBinary_rr<0b0010, 0b01, 0b000, "sadd">;
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def AADD : RVPBinary_rr<0b0011, 0b01, 0b000, "aadd">;
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def SADDU : RVPBinary_rr<0b0110, 0b01, 0b000, "saddu">;
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def AADDU : RVPBinary_rr<0b0111, 0b01, 0b000, "aaddu">;
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def SSUB : RVPBinary_rr<0b1010, 0b01, 0b000, "ssub">;
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def ASUB : RVPBinary_rr<0b1011, 0b01, 0b000, "asub">;
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def SSUBU : RVPBinary_rr<0b1110, 0b01, 0b000, "ssubu">;
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def ASUBU : RVPBinary_rr<0b1111, 0b01, 0b000, "asubu">;
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} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
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let Predicates = [HasStdExtP, IsRV64] in {
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def PADD_W : RVPBinary_rr<0b0000, 0b01, 0b000, "padd.w">;
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def PSADD_W : RVPBinary_rr<0b0010, 0b01, 0b000, "psadd.w">;
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def PAADD_W : RVPBinary_rr<0b0011, 0b01, 0b000, "paadd.w">;
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def PSADDU_W : RVPBinary_rr<0b0110, 0b01, 0b000, "psaddu.w">;
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def PAADDU_W : RVPBinary_rr<0b0111, 0b01, 0b000, "paaddu.w">;
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def PSUB_W : RVPBinary_rr<0b1000, 0b01, 0b000, "psub.w">;
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def PSSUB_W : RVPBinary_rr<0b1010, 0b01, 0b000, "pssub.w">;
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def PASUB_W : RVPBinary_rr<0b1011, 0b01, 0b000, "pasub.w">;
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def PSSUBU_W : RVPBinary_rr<0b1110, 0b01, 0b000, "pssubu.w">;
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def PASUBU_W : RVPBinary_rr<0b1111, 0b01, 0b000, "pasubu.w">;
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} // Predicates = [HasStdExtP, IsRV64]
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let Predicates = [HasStdExtP] in {
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def SLX : RVPBinary_rr<0b0001, 0b11, 0b001, "slx">;
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def PMUL_H_B01 : RVPBinary_rr<0b0010, 0b00, 0b001, "pmul.h.b01">;
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def MVM : RVPBinary_rr<0b0101, 0b00, 0b001, "mvm">;
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def MVMN : RVPBinary_rr<0b0101, 0b01, 0b001, "mvmn">;
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def MERGE : RVPBinary_rr<0b0101, 0b10, 0b001, "merge">;
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def SRX : RVPBinary_rr<0b0101, 0b11, 0b001, "srx">;
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def PMULU_H_B01 : RVPBinary_rr<0b0110, 0b00, 0b001, "pmulu.h.b01">;
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def PDIFSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pdifsumu.b">;
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def PDIFSUMAU_B : RVPBinary_rr<0b0111, 0b10, 0b001, "pdifsumau.b">;
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} // Predicates = [HasStdExtP]
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let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
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def MUL_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "mul.h01">;
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def MACC_H01 : RVPBinary_rr<0b0011, 0b01, 0b001, "macc.h01">;
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def MULU_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "mulu.h01">;
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def MACCU_H01 : RVPBinary_rr<0b0111, 0b01, 0b001, "maccu.h01">;
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} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
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let Predicates = [HasStdExtP, IsRV64] in {
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def PMUL_W_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "pmul.w.h01">;
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def MUL_W01 : RVPBinary_rr<0b0010, 0b11, 0b001, "mul.w01">;
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def PMACC_W_H01 : RVPBinary_rr<0b0011, 0b01, 0b001, "pmacc.w.h01">;
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def MACC_W01 : RVPBinary_rr<0b0011, 0b11, 0b001, "macc.w01">;
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def PMULU_W_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "pmulu.w.h01">;
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def MULU_W01 : RVPBinary_rr<0b0110, 0b11, 0b001, "mulu.w01">;
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def PMACCU_W_H01 : RVPBinary_rr<0b0111, 0b01, 0b001, "pmaccu.w.h01">;
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def MACCU_W01 : RVPBinary_rr<0b0111, 0b11, 0b001, "maccu.w01">;
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} // Predicates = [HasStdExtP, IsRV64]
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// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.
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// Here we include the 0 in the f field to reduce number of tablegen classes.
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let Predicates = [HasStdExtP] in {
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def PSH1ADD_H : RVPBinary_rr<0b0100, 0b00, 0b010, "psh1add.h">;
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def PSSH1SADD_H : RVPBinary_rr<0b0110, 0b00, 0b010, "pssh1sadd.h">;
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} // Predicates = [HasStdExtP]
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let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
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def SSH1SADD : RVPBinary_rr<0b0110, 0b01, 0b010, "ssh1sadd">;
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} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
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let Predicates = [HasStdExtP, IsRV64] in {
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def PSH1ADD_W : RVPBinary_rr<0b0100, 0b01, 0b010, "psh1add.w">;
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def PSSH1SADD_W : RVPBinary_rr<0b0110, 0b01, 0b010, "pssh1sadd.w">;
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def UNZIP8P : RVPBinary_rr<0b1100, 0b00, 0b010, "unzip8p">;
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def UNZIP16P : RVPBinary_rr<0b1100, 0b01, 0b010, "unzip16p">;
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def UNZIP8HP : RVPBinary_rr<0b1100, 0b10, 0b010, "unzip8hp">;
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def UNZIP16HP : RVPBinary_rr<0b1100, 0b11, 0b010, "unzip16hp">;
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def ZIP8P : RVPBinary_rr<0b1110, 0b00, 0b010, "zip8p">;
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def ZIP16P : RVPBinary_rr<0b1110, 0b01, 0b010, "zip16p">;
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def ZIP8HP : RVPBinary_rr<0b1110, 0b10, 0b010, "zip8hp">;
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def ZIP16HP : RVPBinary_rr<0b1110, 0b11, 0b010, "zip16hp">;
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} // Predicates = [HasStdExtP, IsRV64]
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let Predicates = [HasStdExtP] in {
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def PMUL_H_B00 : RVPBinary_rr<0b0000, 0b00, 0b011, "pmul.h.b00">;
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def PMUL_H_B11 : RVPBinary_rr<0b0010, 0b00, 0b011, "pmul.h.b11">;
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def PMULU_H_B00 : RVPBinary_rr<0b0100, 0b00, 0b011, "pmulu.h.b00">;
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def PMULU_H_B11 : RVPBinary_rr<0b0110, 0b00, 0b011, "pmulu.h.b11">;
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def PMULSU_H_B00 : RVPBinary_rr<0b1100, 0b00, 0b011, "pmulsu.h.b00">;
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def PMULSU_H_B11 : RVPBinary_rr<0b1110, 0b00, 0b011, "pmulsu.h.b11">;
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} // Predicates = [HasStdExtP]
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let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
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def MUL_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "mul.h00">;
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def MACC_H00 : RVPBinary_rr<0b0001, 0b01, 0b011, "macc.h00">;
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def MUL_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "mul.h11">;
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def MACC_H11 : RVPBinary_rr<0b0011, 0b01, 0b011, "macc.h11">;
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def MULU_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "mulu.h00">;
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def MACCU_H00 : RVPBinary_rr<0b0101, 0b01, 0b011, "maccu.h00">;
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def MULU_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "mulu.h11">;
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def MACCU_H11 : RVPBinary_rr<0b0111, 0b01, 0b011, "maccu.h11">;
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def MULSU_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "mulsu.h00">;
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def MACCSU_H00 : RVPBinary_rr<0b1101, 0b01, 0b011, "maccsu.h00">;
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def MULSU_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "mulsu.h11">;
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def MACCSU_H11 : RVPBinary_rr<0b1111, 0b01, 0b011, "maccsu.h11">;
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} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
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let Predicates = [HasStdExtP, IsRV64] in {
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def PMUL_W_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "pmul.w.h00">;
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def MUL_W00 : RVPBinary_rr<0b0000, 0b11, 0b011, "mul.w00">;
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def PMACC_W_H00 : RVPBinary_rr<0b0001, 0b01, 0b011, "pmacc.w.h00">;
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def MACC_W00 : RVPBinary_rr<0b0001, 0b11, 0b011, "macc.w00">;
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def PMUL_W_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "pmul.w.h11">;
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def MUL_W11 : RVPBinary_rr<0b0010, 0b11, 0b011, "mul.w11">;
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def PMACC_W_H11 : RVPBinary_rr<0b0011, 0b01, 0b011, "pmacc.w.h11">;
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def MACC_W11 : RVPBinary_rr<0b0011, 0b11, 0b011, "macc.w11">;
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def PMULU_W_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "pmulu.w.h00">;
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def MULU_W00 : RVPBinary_rr<0b0100, 0b11, 0b011, "mulu.w00">;
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def PMACCU_W_H00 : RVPBinary_rr<0b0101, 0b01, 0b011, "pmaccu.w.h00">;
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def MACCU_W00 : RVPBinary_rr<0b0101, 0b11, 0b011, "maccu.w00">;
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def PMULU_W_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "pmulu.w.h11">;
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def MULU_W11 : RVPBinary_rr<0b0110, 0b11, 0b011, "mulu.w11">;
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def PMACCU_W_H11 : RVPBinary_rr<0b0111, 0b01, 0b011, "pmaccu.w.h11">;
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def MACCU_W11 : RVPBinary_rr<0b0111, 0b11, 0b011, "maccu.w11">;
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def PMULSU_W_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "pmulsu.w.h00">;
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def MULSU_W00 : RVPBinary_rr<0b1100, 0b11, 0b011, "mulsu.w00">;
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def PMACCSU_W_H00 : RVPBinary_rr<0b1101, 0b01, 0b011, "pmaccsu.w.h00">;
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def MACCSU_W00 : RVPBinary_rr<0b1101, 0b11, 0b011, "maccsu.w00">;
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def PMULSU_W_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "pmulsu.w.h11">;
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def MULSU_W11 : RVPBinary_rr<0b1110, 0b11, 0b011, "mulsu.w11">;
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def PMACCSU_W_H11 : RVPBinary_rr<0b1111, 0b01, 0b011, "pmaccsu.w.h11">;
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def MACCSU_W11 : RVPBinary_rr<0b1111, 0b11, 0b011, "maccsu.w11">;
519+
} // Predicates = [HasStdExtP, IsRV64]
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// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.
522+
// Here we include the 0 in the f field to reduce number of tablegen classes.
523+
let Predicates = [HasStdExtP] in {
524+
def PPACK_H : RVPBinary_rr<0b0000, 0b00, 0b100, "ppack.h">;
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def PPACKBT_H : RVPBinary_rr<0b0010, 0b00, 0b100, "ppackbt.h">;
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def PPACKTB_H : RVPBinary_rr<0b0100, 0b00, 0b100, "ppacktb.h">;
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def PPACKT_H : RVPBinary_rr<0b0110, 0b00, 0b100, "ppackt.h">;
531+
} // Predicates = [HasStdExtP]
532+
let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
533+
def PACKBT_RV32 : RVPBinary_rr<0b0010, 0b01, 0b100, "packbt">;
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def PACKTB_RV32 : RVPBinary_rr<0b0100, 0b01, 0b100, "packtb">;
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def PACKT_RV32 : RVPBinary_rr<0b0110, 0b01, 0b100, "packt">;
538+
} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
539+
let Predicates = [HasStdExtP, IsRV64] in {
540+
def PPACK_W : RVPBinary_rr<0b0000, 0b01, 0b100, "ppack.w">;
541+
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def PPACKBT_W : RVPBinary_rr<0b0010, 0b01, 0b100, "ppackbt.w">;
543+
def PACKBT_RV64 : RVPBinary_rr<0b0010, 0b11, 0b100, "packbt">;
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def PPACKTB_W : RVPBinary_rr<0b0100, 0b01, 0b100, "ppacktb.w">;
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def PACKTB_RV64 : RVPBinary_rr<0b0100, 0b11, 0b100, "packtb">;
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def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;
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def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;
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} // Predicates = [HasStdExtP, IsRV64]

‎llvm/test/MC/RISCV/rv32p-invalid.s‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,3 +45,64 @@ psrl.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the follow
4545
predsum.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
4646
predsumu.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
4747
psra.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
48+
49+
padd.w t3, s0, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
50+
psadd.w t3, t1, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
51+
paadd.w t5, t1, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
52+
psaddu.w s0, s2, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
53+
paaddu.w s0, t1, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
54+
psub.w t3, a0, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
55+
pssub.w t3, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
56+
pasub.w t3, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
57+
pssubu.w a0, a4, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
58+
pasubu.w a0, t3, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
59+
60+
pmul.w.h01 s2, t5, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
61+
mul.w01 t5, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
62+
pmacc.w.h01 t1, t1, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
63+
macc.w01 s2, a0, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
64+
pmulu.w.h01 t1, a4, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
65+
mulu.w01 t5, t1, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
66+
pmaccu.w.h01 t5, t5, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
67+
maccu.w01 a0, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
68+
69+
psh1add.w s2, t5, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
70+
pssh1sadd.w a4, t3, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
71+
unzip8p a4, t3, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
72+
unzip16p t5, a4, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
73+
unzip8hp s0, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
74+
unzip16hp a0, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
75+
zip8p t5, t3, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
76+
zip16p a0, t5, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
77+
zip8hp t5, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
78+
zip16hp t1, t5, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
79+
80+
pmul.w.h00 s2, t1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
81+
mul.w00 a4, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
82+
pmacc.w.h00 s2, t5, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
83+
macc.w00 t1, a0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
84+
pmul.w.h11 s0, a4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
85+
mul.w11 a0, t3, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
86+
pmacc.w.h11 a4, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
87+
macc.w11 t3, s2, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
88+
pmulu.w.h00 a2, t3, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
89+
mulu.w00 a0, t5, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
90+
pmaccu.w.h00 t3, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
91+
maccu.w00 s2, t1, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
92+
pmulu.w.h11 s0, t5, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
93+
mulu.w11 s0, t1, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
94+
pmaccu.w.h11 a0, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
95+
maccu.w11 s2, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
96+
pmulsu.w.h00 t5, t5, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
97+
mulsu.w00 t1, s0, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
98+
pmulsu.w.h11 t1, t3, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
99+
mulsu.w11 a2, s2, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
100+
pmaccsu.w.h00 a4, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
101+
maccsu.w00 a4, s2, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
102+
pmaccsu.w.h11 a0, a2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
103+
maccsu.w11 t5, a4, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
104+
105+
ppack.w t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
106+
ppackbt.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
107+
ppacktb.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
108+
ppackt.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

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