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s-barannikovs-barannikov
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Revert VLD/VST opcodes
1 parent f704a1a commit 06863f3

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3 files changed

+80
-45
lines changed

3 files changed

+80
-45
lines changed

‎llvm/lib/Target/ARM/ARMInstrMVE.td‎

Lines changed: 9 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -6055,49 +6055,13 @@ foreach wb = [MVE_vldst24_writeback<
60556055
"vst" # n.nvecs # stage # "." # s.lanesize>;
60566056
}
60576057

6058-
// Vector load N-element structure to all lanes
6059-
def MVE_VLD1DUP : SDNode<"ARMISD::VLD1DUP", SDTypeProfile<1, 2, []>, [SDNPHasChain, SDNPMemOperand]>;
6060-
def MVE_VLD2DUP : SDNode<"ARMISD::VLD2DUP", SDTypeProfile<2, 1, []>, [SDNPHasChain, SDNPMemOperand]>;
6061-
def MVE_VLD3DUP : SDNode<"ARMISD::VLD3DUP", SDTypeProfile<3, 1, []>, [SDNPHasChain, SDNPMemOperand]>;
6062-
def MVE_VLD4DUP : SDNode<"ARMISD::VLD4DUP", SDTypeProfile<4, 1, []>, [SDNPHasChain, SDNPMemOperand]>;
6063-
6064-
// NEON loads with post-increment base updates
6065-
def MVE_VLD1_UPD : SDNode<"ARMISD::VLD1_UPD", SDTypeProfile<2, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6066-
def MVE_VLD2_UPD : SDNode<"ARMISD::VLD2_UPD", SDTypeProfile<3, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6067-
def MVE_VLD3_UPD : SDNode<"ARMISD::VLD3_UPD", SDTypeProfile<4, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6068-
def MVE_VLD4_UPD : SDNode<"ARMISD::VLD4_UPD", SDTypeProfile<5, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6069-
def MVE_VLD2LN_UPD : SDNode<"ARMISD::VLD2LN_UPD", SDTypeProfile<3, 6, []>, [SDNPHasChain, SDNPMemOperand]>;
6070-
def MVE_VLD3LN_UPD : SDNode<"ARMISD::VLD3LN_UPD", SDTypeProfile<4, 7, []>, [SDNPHasChain, SDNPMemOperand]>;
6071-
def MVE_VLD4LN_UPD : SDNode<"ARMISD::VLD4LN_UPD", SDTypeProfile<5, 8, []>, [SDNPHasChain, SDNPMemOperand]>;
6072-
def MVE_VLD1DUP_UPD : SDNode<"ARMISD::VLD1DUP_UPD", SDTypeProfile<2, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6073-
def MVE_VLD2DUP_UPD : SDNode<"ARMISD::VLD2DUP_UPD", SDTypeProfile<3, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6074-
def MVE_VLD3DUP_UPD : SDNode<"ARMISD::VLD3DUP_UPD", SDTypeProfile<4, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6075-
def MVE_VLD4DUP_UPD : SDNode<"ARMISD::VLD4DUP_UPD", SDTypeProfile<5, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6076-
def MVE_VLD1x2_UPD : SDNode<"ARMISD::VLD1x2_UPD", SDTypeProfile<3, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6077-
def MVE_VLD1x3_UPD : SDNode<"ARMISD::VLD1x3_UPD", SDTypeProfile<4, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6078-
def MVE_VLD1x4_UPD : SDNode<"ARMISD::VLD1x4_UPD", SDTypeProfile<5, 3, []>, [SDNPHasChain, SDNPMemOperand]>;
6079-
6080-
def SDTARMVST1 : SDTypeProfile<1, 4, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
6081-
SDTCisVT<4, i32>]>;
6082-
def SDTARMVST2 : SDTypeProfile<1, 5, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
6083-
SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>;
6084-
def SDTARMVST3 : SDTypeProfile<1, 6, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
6085-
SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>, SDTCisVT<6, i32>]>;
6086-
def SDTARMVST4 : SDTypeProfile<1, 7, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
6087-
SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>,
6088-
SDTCisSameAs<3, 6>, SDTCisVT<7, i32>]>;
6089-
6090-
// NEON stores with post-increment base updates
6091-
def MVE_VST1_UPD : SDNode<"ARMISD::VST1_UPD", SDTARMVST1, [SDNPHasChain, SDNPMemOperand]>;
6092-
def MVE_VST2_UPD : SDNode<"ARMISD::VST2_UPD", SDTARMVST2, [SDNPHasChain, SDNPMemOperand]>;
6093-
def MVE_VST3_UPD : SDNode<"ARMISD::VST3_UPD", SDTARMVST3, [SDNPHasChain, SDNPMemOperand]>;
6094-
def MVE_VST4_UPD : SDNode<"ARMISD::VST4_UPD", SDTARMVST4, [SDNPHasChain, SDNPMemOperand]>;
6095-
def MVE_VST2LN_UPD : SDNode<"ARMISD::VST2LN_UPD", SDTypeProfile<1, 6, []>, [SDNPHasChain, SDNPMemOperand]>;
6096-
def MVE_VST3LN_UPD : SDNode<"ARMISD::VST3LN_UPD", SDTypeProfile<1, 7, []>, [SDNPHasChain, SDNPMemOperand]>;
6097-
def MVE_VST4LN_UPD : SDNode<"ARMISD::VST4LN_UPD", SDTypeProfile<1, 8, []>, [SDNPHasChain, SDNPMemOperand]>;
6098-
def MVE_VST1x2_UPD : SDNode<"ARMISD::VST1x2_UPD", SDTypeProfile<1, 5, []>, [SDNPHasChain, SDNPMemOperand]>;
6099-
def MVE_VST1x3_UPD : SDNode<"ARMISD::VST1x3_UPD", SDTypeProfile<1, 6, []>, [SDNPHasChain, SDNPMemOperand]>;
6100-
def MVE_VST1x4_UPD : SDNode<"ARMISD::VST1x4_UPD", SDTypeProfile<1, 7, []>, [SDNPHasChain, SDNPMemOperand]>;
6058+
def SDTARMVST2 : SDTypeProfile<1, 5, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
6059+
SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>;
6060+
def SDTARMVST4 : SDTypeProfile<1, 7, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
6061+
SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>,
6062+
SDTCisSameAs<3, 6>, SDTCisVT<7, i32>]>;
6063+
def MVEVST2UPD : SDNode<"ARMISD::VST2_UPD", SDTARMVST2, [SDNPHasChain, SDNPMemOperand]>;
6064+
def MVEVST4UPD : SDNode<"ARMISD::VST4_UPD", SDTARMVST4, [SDNPHasChain, SDNPMemOperand]>;
61016065

61026066
multiclass MVE_vst24_patterns<int lanesize, ValueType VT> {
61036067
foreach stage = [0,1] in
@@ -6107,7 +6071,7 @@ multiclass MVE_vst24_patterns<int lanesize, ValueType VT> {
61076071
(REG_SEQUENCE MQQPR, VT:$v0, qsub_0, VT:$v1, qsub_1),
61086072
t2_addr_offset_none:$addr)>;
61096073
foreach stage = [0,1] in
6110-
def : Pat<(i32 (MVE_VST2_UPD i32:$addr, (i32 32),
6074+
def : Pat<(i32 (MVEVST2UPD i32:$addr, (i32 32),
61116075
(VT MQPR:$v0), (VT MQPR:$v1), (i32 stage))),
61126076
(i32 (!cast<Instruction>("MVE_VST2"#stage#"_"#lanesize#_wb)
61136077
(REG_SEQUENCE MQQPR, VT:$v0, qsub_0, VT:$v1, qsub_1),
@@ -6122,7 +6086,7 @@ multiclass MVE_vst24_patterns<int lanesize, ValueType VT> {
61226086
VT:$v2, qsub_2, VT:$v3, qsub_3),
61236087
t2_addr_offset_none:$addr)>;
61246088
foreach stage = [0,1,2,3] in
6125-
def : Pat<(i32 (MVE_VST4_UPD i32:$addr, (i32 64),
6089+
def : Pat<(i32 (MVEVST4UPD i32:$addr, (i32 64),
61266090
(VT MQPR:$v0), (VT MQPR:$v1),
61276091
(VT MQPR:$v2), (VT MQPR:$v3), (i32 stage))),
61286092
(i32 (!cast<Instruction>("MVE_VST4"#stage#"_"#lanesize#_wb)

‎llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,12 +50,47 @@ const char *ARMSelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
5050
MAKE_CASE(ARMISD::MVEZEXT)
5151
MAKE_CASE(ARMISD::MVETRUNC)
5252
MAKE_CASE(ARMISD::BUILD_VECTOR)
53+
MAKE_CASE(ARMISD::VLD1DUP)
54+
MAKE_CASE(ARMISD::VLD2DUP)
55+
MAKE_CASE(ARMISD::VLD3DUP)
56+
MAKE_CASE(ARMISD::VLD4DUP)
57+
MAKE_CASE(ARMISD::VLD1_UPD)
58+
MAKE_CASE(ARMISD::VLD2_UPD)
59+
MAKE_CASE(ARMISD::VLD3_UPD)
60+
MAKE_CASE(ARMISD::VLD4_UPD)
61+
MAKE_CASE(ARMISD::VLD1x2_UPD)
62+
MAKE_CASE(ARMISD::VLD1x3_UPD)
63+
MAKE_CASE(ARMISD::VLD1x4_UPD)
64+
MAKE_CASE(ARMISD::VLD2LN_UPD)
65+
MAKE_CASE(ARMISD::VLD3LN_UPD)
66+
MAKE_CASE(ARMISD::VLD4LN_UPD)
67+
MAKE_CASE(ARMISD::VLD1DUP_UPD)
68+
MAKE_CASE(ARMISD::VLD2DUP_UPD)
69+
MAKE_CASE(ARMISD::VLD3DUP_UPD)
70+
MAKE_CASE(ARMISD::VLD4DUP_UPD)
71+
MAKE_CASE(ARMISD::VST1_UPD)
72+
MAKE_CASE(ARMISD::VST3_UPD)
73+
MAKE_CASE(ARMISD::VST1x2_UPD)
74+
MAKE_CASE(ARMISD::VST1x3_UPD)
75+
MAKE_CASE(ARMISD::VST1x4_UPD)
76+
MAKE_CASE(ARMISD::VST2LN_UPD)
77+
MAKE_CASE(ARMISD::VST3LN_UPD)
78+
MAKE_CASE(ARMISD::VST4LN_UPD)
5379
}
5480
#undef MAKE_CASE
5581

5682
return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
5783
}
5884

85+
bool ARMSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
86+
// These nodes don't have corresponding entries in *.td files yet.
87+
if (Opcode >= ARMISD::FIRST_MEMORY_OPCODE &&
88+
Opcode <= ARMISD::LAST_MEMORY_OPCODE)
89+
return true;
90+
91+
return SelectionDAGGenTargetInfo::isTargetMemoryOpcode(Opcode);
92+
}
93+
5994
void ARMSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
6095
const SDNode *N) const {
6196
switch (N->getOpcode()) {

‎llvm/lib/Target/ARM/ARMSelectionDAGInfo.h‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,40 @@ enum NodeType : unsigned {
3636
// operands need to be legalized. Define an ARM-specific version of
3737
// BUILD_VECTOR for this purpose.
3838
BUILD_VECTOR,
39+
40+
// Vector load N-element structure to all lanes:
41+
FIRST_MEMORY_OPCODE,
42+
VLD1DUP = FIRST_MEMORY_OPCODE,
43+
VLD2DUP,
44+
VLD3DUP,
45+
VLD4DUP,
46+
47+
// NEON loads with post-increment base updates:
48+
VLD1_UPD,
49+
VLD2_UPD,
50+
VLD3_UPD,
51+
VLD4_UPD,
52+
VLD2LN_UPD,
53+
VLD3LN_UPD,
54+
VLD4LN_UPD,
55+
VLD1DUP_UPD,
56+
VLD2DUP_UPD,
57+
VLD3DUP_UPD,
58+
VLD4DUP_UPD,
59+
VLD1x2_UPD,
60+
VLD1x3_UPD,
61+
VLD1x4_UPD,
62+
63+
// NEON stores with post-increment base updates:
64+
VST1_UPD,
65+
VST3_UPD,
66+
VST2LN_UPD,
67+
VST3LN_UPD,
68+
VST4LN_UPD,
69+
VST1x2_UPD,
70+
VST1x3_UPD,
71+
VST1x4_UPD,
72+
LAST_MEMORY_OPCODE = VST1x4_UPD,
3973
};
4074

4175
} // namespace ARMISD
@@ -62,6 +96,8 @@ class ARMSelectionDAGInfo : public SelectionDAGGenTargetInfo {
6296

6397
const char *getTargetNodeName(unsigned Opcode) const override;
6498

99+
bool isTargetMemoryOpcode(unsigned Opcode) const override;
100+
65101
void verifyTargetNode(const SelectionDAG &DAG,
66102
const SDNode *N) const override;
67103

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