[RISCV] Select unsigned bitfiled extracts for XAndesPerf

The XAndesPerf extension includes unsigned bitfield extraction instruction
`NDS.BFOZ`, which can extract the bits from LSB to MSB, places them starting
at bit 0, and zero-extends the result.

Author: tclin914

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -672,14 +672,17 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
 bool RISCVDAGToDAGISel::tryUnsignedBitfieldExtract(SDNode *Node, SDLoc DL,
                                                    MVT VT, SDValue X,
                                                    unsigned Msb, unsigned Lsb) {
-  // Only supported with XTHeadBb at the moment.
-  if (!Subtarget->hasVendorXTHeadBb())
+  // Only supported with XTHeadBb/XAndesPerf at the moment.
+  if (!Subtarget->hasVendorXTHeadBb() && !Subtarget->hasVendorXAndesPerf())
     return false;
 
-  SDNode *TH_EXTU = CurDAG->getMachineNode(
-      RISCV::TH_EXTU, DL, VT, X, CurDAG->getTargetConstant(Msb, DL, VT),
-      CurDAG->getTargetConstant(Lsb, DL, VT));
-  ReplaceNode(Node, TH_EXTU);
+  unsigned Opc =
+      Subtarget->hasVendorXTHeadBb() ? RISCV::TH_EXTU : RISCV::NDS_BFOZ;
+
+  SDNode *Ube = CurDAG->getMachineNode(Opc, DL, VT, X,
+                                       CurDAG->getTargetConstant(Msb, DL, VT),
+                                       CurDAG->getTargetConstant(Lsb, DL, VT));
+  ReplaceNode(Node, Ube);
   return true;
 }
 

llvm/test/CodeGen/RISCV/rv32xandesperf.ll

@@ -5,8 +5,7 @@
 define i32 @bfoz_from_and_i32(i32 %x) {
 ; CHECK-LABEL: bfoz_from_and_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 20
-; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    ret
   %a = and i32 %x, 4095
   ret i32 %a
@@ -16,8 +15,7 @@ define i64 @bfoz_from_and_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_and_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $x11 killed $x10
-; CHECK-NEXT:    slli a0, a0, 20
-; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    ret
   %a = and i64 %x, 4095
@@ -27,8 +25,7 @@ define i64 @bfoz_from_and_i64(i64 %x) {
 define i32 @bfoz_from_and_lshr_i32(i32 %x) {
 ; CHECK-LABEL: bfoz_from_and_lshr_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 6
-; CHECK-NEXT:    srli a0, a0, 29
+; CHECK-NEXT:    nds.bfoz a0, a0, 25, 23
 ; CHECK-NEXT:    ret
   %shifted = lshr i32 %x, 23
   %masked = and i32 %shifted, 7
@@ -39,8 +36,7 @@ define i64 @bfoz_from_and_lshr_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_and_lshr_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $x12 killed $x11
-; CHECK-NEXT:    slli a0, a1, 6
-; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    nds.bfoz a0, a1, 25, 14
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:    ret
   %shifted = lshr i64 %x, 46
@@ -51,8 +47,7 @@ define i64 @bfoz_from_and_lshr_i64(i64 %x) {
 define i32 @bfoz_from_lshr_and_i32(i32 %x) {
 ; CHECK-LABEL: bfoz_from_lshr_and_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 8
-; CHECK-NEXT:    srli a0, a0, 20
+; CHECK-NEXT:    nds.bfoz a0, a0, 23, 12
 ; CHECK-NEXT:    ret
   %masked = and i32 %x, 16773120
   %shifted = lshr i32 %masked, 12

llvm/test/CodeGen/RISCV/rv64xandesperf.ll

@@ -5,8 +5,7 @@
 define i32 @bfoz_from_and_i32(i32 %x) {
 ; CHECK-LABEL: bfoz_from_and_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 52
-; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    ret
   %a = and i32 %x, 4095
   ret i32 %a
@@ -15,8 +14,7 @@ define i32 @bfoz_from_and_i32(i32 %x) {
 define i64 @bfoz_from_and_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_and_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 52
-; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
 ; CHECK-NEXT:    ret
   %a = and i64 %x, 4095
   ret i64 %a
@@ -25,8 +23,7 @@ define i64 @bfoz_from_and_i64(i64 %x) {
 define i32 @bfoz_from_and_lshr_i32(i32 %x) {
 ; CHECK-LABEL: bfoz_from_and_lshr_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 38
-; CHECK-NEXT:    srli a0, a0, 61
+; CHECK-NEXT:    nds.bfoz a0, a0, 25, 23
 ; CHECK-NEXT:    ret
   %shifted = lshr i32 %x, 23
   %masked = and i32 %shifted, 7
@@ -36,8 +33,7 @@ define i32 @bfoz_from_and_lshr_i32(i32 %x) {
 define i64 @bfoz_from_and_lshr_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_and_lshr_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 6
-; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    nds.bfoz a0, a0, 57, 46
 ; CHECK-NEXT:    ret
   %shifted = lshr i64 %x, 46
   %masked = and i64 %shifted, 4095
@@ -47,8 +43,7 @@ define i64 @bfoz_from_and_lshr_i64(i64 %x) {
 define i32 @bfoz_from_lshr_and_i32(i32 %x) {
 ; CHECK-LABEL: bfoz_from_lshr_and_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 40
-; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    nds.bfoz a0, a0, 23, 12
 ; CHECK-NEXT:    ret
   %masked = and i32 %x, 16773120
   %shifted = lshr i32 %masked, 12
@@ -58,8 +53,7 @@ define i32 @bfoz_from_lshr_and_i32(i32 %x) {
 define i64 @bfoz_from_lshr_and_i64(i64 %x) {
 ; CHECK-LABEL: bfoz_from_lshr_and_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slli a0, a0, 28
-; CHECK-NEXT:    srli a0, a0, 52
+; CHECK-NEXT:    nds.bfoz a0, a0, 35, 24
 ; CHECK-NEXT:    ret
   %masked = and i64 %x, 68702699520
   %shifted = lshr i64 %masked, 24