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davemgreendavemgreen
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[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594)
This allows us to easily detect, without known-bits, that the or in a fshl/fshr is disjoint allowing us to use usra under aarch64.
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10 files changed

+224
-288
lines changed

10 files changed

+224
-288
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7264,7 +7264,7 @@ LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) {
72647264
}
72657265
}
72667266

7267-
MIRBuilder.buildOr(Dst, ShX, ShY);
7267+
MIRBuilder.buildOr(Dst, ShX, ShY, MachineInstr::Disjoint);
72687268
MI.eraseFromParent();
72697269
return Legalized;
72707270
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1027,9 +1027,9 @@ def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
10271027
return CurDAG->isADDLike(SDValue(N,0));
10281028
}]> {
10291029
let GISelPredicateCode = [{
1030-
// Only handle G_ADD for now. FIXME. build capability to compute whether
1031-
// operands of G_OR have common bits set or not.
1032-
return MI.getOpcode() == TargetOpcode::G_ADD;
1030+
return MI.getOpcode() == TargetOpcode::G_ADD ||
1031+
(MI.getOpcode() == TargetOpcode::G_OR &&
1032+
MI.getFlag(MachineInstr::MIFlag::Disjoint));
10331033
}];
10341034
}
10351035

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ body: |
2828
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s64)
2929
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
3030
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
31-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
31+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
3232
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
3333
; CHECK-NEXT: RET_ReallyLR implicit $w0
3434
%3:_(s32) = COPY $w0
@@ -71,7 +71,7 @@ body: |
7171
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s64)
7272
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
7373
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
74-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
74+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
7575
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
7676
; CHECK-NEXT: RET_ReallyLR implicit $w0
7777
%3:_(s32) = COPY $w0
@@ -110,7 +110,7 @@ body: |
110110
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
111111
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s64)
112112
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32)
113-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
113+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
114114
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
115115
; CHECK-NEXT: RET_ReallyLR implicit $w0
116116
%0:_(s32) = COPY $w0
@@ -145,7 +145,7 @@ body: |
145145
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
146146
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s64)
147147
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND1]](s64)
148-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR1]]
148+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]]
149149
; CHECK-NEXT: $x0 = COPY [[OR]](s64)
150150
; CHECK-NEXT: RET_ReallyLR implicit $x0
151151
%0:_(s64) = COPY $x0
@@ -175,7 +175,7 @@ body: |
175175
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
176176
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
177177
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s64)
178-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
178+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
179179
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
180180
; CHECK-NEXT: RET_ReallyLR implicit $w0
181181
%2:_(s32) = COPY $w0
@@ -209,7 +209,7 @@ body: |
209209
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
210210
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
211211
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
212-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
212+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
213213
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
214214
; CHECK-NEXT: RET_ReallyLR implicit $w0
215215
%2:_(s32) = COPY $w0
@@ -246,7 +246,7 @@ body: |
246246
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
247247
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
248248
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C3]](s64)
249-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
249+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
250250
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
251251
; CHECK-NEXT: RET_ReallyLR implicit $w0
252252
%2:_(s32) = COPY $w0
@@ -280,7 +280,7 @@ body: |
280280
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
281281
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
282282
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
283-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
283+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
284284
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
285285
; CHECK-NEXT: RET_ReallyLR implicit $w0
286286
%2:_(s32) = COPY $w0
@@ -314,7 +314,7 @@ body: |
314314
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
315315
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
316316
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
317-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
317+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
318318
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
319319
; CHECK-NEXT: RET_ReallyLR implicit $w0
320320
%2:_(s32) = COPY $w0
@@ -351,7 +351,7 @@ body: |
351351
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
352352
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
353353
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C3]](s64)
354-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
354+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
355355
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
356356
; CHECK-NEXT: RET_ReallyLR implicit $w0
357357
%2:_(s32) = COPY $w0
@@ -437,7 +437,7 @@ body: |
437437
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s64)
438438
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
439439
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[C2]](s64)
440-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
440+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
441441
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
442442
; CHECK-NEXT: RET_ReallyLR implicit $w0
443443
%0:_(s32) = COPY $w0
@@ -520,7 +520,7 @@ body: |
520520
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64)
521521
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s64)
522522
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[C]](s64)
523-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR1]]
523+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]]
524524
; CHECK-NEXT: $x0 = COPY [[OR]](s64)
525525
; CHECK-NEXT: RET_ReallyLR implicit $x0
526526
%0:_(s64) = COPY $x0
@@ -556,7 +556,7 @@ body: |
556556
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<4 x s32>)
557557
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY1]], [[BUILD_VECTOR2]](<4 x s32>)
558558
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[LSHR]], [[BUILD_VECTOR1]](<4 x s32>)
559-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[SHL]], [[LSHR1]]
559+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = disjoint G_OR [[SHL]], [[LSHR1]]
560560
; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
561561
; CHECK-NEXT: RET_ReallyLR implicit $q0
562562
%0:_(<4 x s32>) = COPY $q0

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ body: |
2727
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
2828
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
2929
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
30-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
30+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
3131
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
3232
; CHECK-NEXT: RET_ReallyLR implicit $w0
3333
%3:_(s32) = COPY $w0
@@ -69,7 +69,7 @@ body: |
6969
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
7070
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
7171
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
72-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
72+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
7373
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
7474
; CHECK-NEXT: RET_ReallyLR implicit $w0
7575
%3:_(s32) = COPY $w0
@@ -108,7 +108,7 @@ body: |
108108
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
109109
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
110110
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND]](s32)
111-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
111+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
112112
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
113113
; CHECK-NEXT: RET_ReallyLR implicit $w0
114114
%0:_(s32) = COPY $w0
@@ -143,7 +143,7 @@ body: |
143143
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64)
144144
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64)
145145
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[AND]](s64)
146-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
146+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]]
147147
; CHECK-NEXT: $x0 = COPY [[OR]](s64)
148148
; CHECK-NEXT: RET_ReallyLR implicit $x0
149149
%0:_(s64) = COPY $x0
@@ -175,7 +175,7 @@ body: |
175175
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
176176
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
177177
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
178-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
178+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
179179
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
180180
; CHECK-NEXT: RET_ReallyLR implicit $w0
181181
%2:_(s32) = COPY $w0
@@ -209,7 +209,7 @@ body: |
209209
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
210210
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
211211
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
212-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
212+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
213213
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
214214
; CHECK-NEXT: RET_ReallyLR implicit $w0
215215
%2:_(s32) = COPY $w0
@@ -245,7 +245,7 @@ body: |
245245
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
246246
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
247247
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C3]](s64)
248-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
248+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
249249
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
250250
; CHECK-NEXT: RET_ReallyLR implicit $w0
251251
%2:_(s32) = COPY $w0
@@ -279,7 +279,7 @@ body: |
279279
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
280280
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
281281
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
282-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
282+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
283283
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
284284
; CHECK-NEXT: RET_ReallyLR implicit $w0
285285
%2:_(s32) = COPY $w0
@@ -313,7 +313,7 @@ body: |
313313
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
314314
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
315315
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s64)
316-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
316+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
317317
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
318318
; CHECK-NEXT: RET_ReallyLR implicit $w0
319319
%2:_(s32) = COPY $w0
@@ -349,7 +349,7 @@ body: |
349349
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
350350
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
351351
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C3]](s64)
352-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
352+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
353353
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
354354
; CHECK-NEXT: RET_ReallyLR implicit $w0
355355
%2:_(s32) = COPY $w0
@@ -507,7 +507,7 @@ body: |
507507
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C2]](s64)
508508
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[C]](s64)
509509
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C1]](s64)
510-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
510+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]]
511511
; CHECK-NEXT: $x0 = COPY [[OR]](s64)
512512
; CHECK-NEXT: RET_ReallyLR implicit $x0
513513
%0:_(s64) = COPY $x0
@@ -541,7 +541,7 @@ body: |
541541
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR2]](<4 x s32>)
542542
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(<4 x s32>) = G_SHL [[SHL]], [[BUILD_VECTOR1]](<4 x s32>)
543543
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY1]], [[BUILD_VECTOR]](<4 x s32>)
544-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[SHL1]], [[LSHR]]
544+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = disjoint G_OR [[SHL1]], [[LSHR]]
545545
; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
546546
; CHECK-NEXT: RET_ReallyLR implicit $q0
547547
%0:_(<4 x s32>) = COPY $q0

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