Address review

Author: SamTebbs33

llvm/include/llvm/CodeGen/BasicTTIImpl.h

@@ -2192,6 +2192,22 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
     }
     case Intrinsic::loop_dependence_raw_mask:
     case Intrinsic::loop_dependence_war_mask: {
+      // Compute the cost of the expanded version of these intrinsics:
+      //    ; Figure out if there's overlap between the pointers.
+      //    diff = (ptrB - ptrA) / eltSize ; read-after-write will use the
+      //        absolute difference
+      //    cmp = diff <= 0 ; read-after-write will check for equality
+      //        with 0
+      //    ; Create a mask with each lane < diff active. This is essentiallly
+      //        an active lane mask between 0 and diff.
+      //    diff_splat = splat diff to <Y x i64>
+      //    steps = stepvector <Y x i64>
+      //    diff_mask = steps <= diff_splat
+      //    ; OR that diff mask with the comparison result, so that each lane is
+      //        active if it's less than diff or there was no overlap in the
+      //        first place. Otherwise the lane is inactive.
+      //    cmp_splat = splat cmp to <Y x i1>
+      //    result = or cmp_splat diff_mask
       InstructionCost Cost = 0;
       Type *PtrTy = ICA.getArgTypes()[0];
       bool IsReadAfterWrite = IID == Intrinsic::loop_dependence_raw_mask;

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

@@ -1816,6 +1816,22 @@ SDValue VectorLegalizer::ExpandVP_FCOPYSIGN(SDNode *Node) {
 }
 
 SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
+  // Expand these intrinsics:
+  //    ; Figure out if there's overlap between the pointers.
+  //    diff = (ptrB - ptrA) / eltSize ; read-after-write will use the absolute
+  //        difference
+  //    cmp = diff <= 0 ; read-after-write will check for equality
+  //        with 0
+  //    ; Create a mask with each lane < diff active. This is essentiallly an
+  //        active lane mask between 0 and diff.
+  //    diff_splat = splat diff to <Y x i64>
+  //    steps = stepvector <Y x i64>
+  //    diff_mask = steps <= diff_splat
+  //    ; OR that diff mask with the comparison result, so that each lane is
+  //        active if it's less than diff or there was no overlap in the
+  //        first place. Otherwise the lane is inactive.
+  //    cmp_splat = splat cmp to <Y x i1>
+  //    result = or cmp_splat diff_mask
   SDLoc DL(N);
   SDValue SourceValue = N->getOperand(0);
   SDValue SinkValue = N->getOperand(1);

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

@@ -1034,37 +1034,18 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   }
   case Intrinsic::loop_dependence_raw_mask:
   case Intrinsic::loop_dependence_war_mask: {
-    auto *EltSize = cast<ConstantInt>(ICA.getArgs()[2]);
+    unsigned EltSizeInBytes =
+        cast<ConstantInt>(ICA.getArgs()[2])->getZExtValue();
     EVT VecVT = getTLI()->getValueType(DL, RetTy);
     // An invalid element size and return type combination must be expanded.
-    bool MustBeExpanded = false;
-    switch (EltSize->getSExtValue()) {
-    case 1:
-      if (VecVT != MVT::v16i1 && VecVT != MVT::nxv16i1)
-        MustBeExpanded = true;
-      break;
-    case 2:
-      if (VecVT != MVT::v8i1 && VecVT != MVT::nxv8i1)
-        MustBeExpanded = true;
-      break;
-    case 4:
-      if (VecVT != MVT::v4i1 && VecVT != MVT::nxv4i1)
-        MustBeExpanded = true;
-      break;
-    case 8:
-      if (VecVT != MVT::v2i1 && VecVT != MVT::nxv2i1)
-        MustBeExpanded = true;
-      break;
-    default:
-      MustBeExpanded = true;
-      // Other element sizes are incompatible with whilewr/rw, so expand instead
-      break;
-    }
+    bool MustBeExpanded =
+        VecVT.getVectorMinNumElements() != (16 / EltSizeInBytes) ||
+        !isPowerOf2_32(EltSizeInBytes) || EltSizeInBytes > 8;
 
     // The whilewr/rw instructions require SVE2 or SME
-    if (MustBeExpanded || (!ST->hasSVE2() && !ST->hasSME()))
-      break;
-    return 1;
+    if (!MustBeExpanded && (ST->hasSVE2() || ST->hasSME()))
+      return 1;
+    break;
   }
   case Intrinsic::experimental_vector_extract_last_active:
     if (ST->isSVEorStreamingSVEAvailable()) {