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[RISCV][MC] Create an AsmOperand for carry-in vmask (#124317)
Previously we used a fixed assembly string as well as encoding for the carry-in vector mask, since it will always be there. However, this makes both AsmParser and disassembler to either create a garbage MCOperand for the mask or fail to add one as a whole. This wouldn't be a problem for majority of the cases but tools like llvm-mca who relies on MCInst will fail to account for the register dependency on these mask operands.
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5 files changed

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-15
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1681,6 +1681,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
16811681
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
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return Error(ErrorLoc, "operand must be v0.t");
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}
1684+
case Match_InvalidVMaskCarryInRegister: {
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SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
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return Error(ErrorLoc, "operand must be v0");
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}
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case Match_InvalidSImm5Plus1: {
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return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1,
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(1 << 4),

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -297,6 +297,16 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
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return MCDisassembler::Success;
298298
}
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300+
static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(RISCV::V0));
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return MCDisassembler::Success;
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}
309+
300310
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
302312
const MCDisassembler *Decoder) {

‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td‎

Lines changed: 20 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -50,13 +50,25 @@ def VMaskAsmOperand : AsmOperandClass {
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let DiagnosticType = "InvalidVMaskRegister";
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}
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53+
def VMaskCarryInAsmOperand : AsmOperandClass {
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let Name = "RVVMaskCarryInRegOpOperand";
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let RenderMethod = "addRegOperands";
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let PredicateMethod = "isV0Reg";
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let DiagnosticType = "InvalidVMaskCarryInRegister";
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}
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def VMaskOp : RegisterOperand<VMV0> {
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let ParserMatchClass = VMaskAsmOperand;
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let PrintMethod = "printVMaskReg";
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let EncoderMethod = "getVMaskReg";
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let DecoderMethod = "decodeVMaskReg";
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}
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def VMaskCarryInOp : RegisterOperand<VMV0> {
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let ParserMatchClass = VMaskCarryInAsmOperand;
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let EncoderMethod = "getVMaskReg";
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}
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def simm5 : RISCVSImmLeafOp<5> {
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let MCOperandPredicate = [{
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int64_t Imm;
@@ -442,10 +454,8 @@ class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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// op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
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class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVV<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, VR:$vs1, VMV0:$v0),
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opcodestr, "$vd, $vs2, $vs1, v0"> {
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let vm = 0;
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}
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(ins VR:$vs2, VR:$vs1, VMaskCarryInOp:$vm),
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opcodestr, "$vd, $vs2, $vs1, $vm">;
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// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
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class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr,
@@ -474,10 +484,8 @@ class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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// op vd, vs2, rs1, v0 (without mask, use v0 as carry input)
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class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVX<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, GPR:$rs1, VMV0:$v0),
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opcodestr, "$vd, $vs2, $rs1, v0"> {
479-
let vm = 0;
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}
487+
(ins VR:$vs2, GPR:$rs1, VMaskCarryInOp:$vm),
488+
opcodestr, "$vd, $vs2, $rs1, $vm">;
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482490
// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
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class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
@@ -506,10 +514,8 @@ class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
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// op vd, vs2, imm, v0 (without mask, use v0 as carry input)
507515
class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
508516
: RVInstIVI<funct6, (outs VR:$vd),
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(ins VR:$vs2, optype:$imm, VMV0:$v0),
510-
opcodestr, "$vd, $vs2, $imm, v0"> {
511-
let vm = 0;
512-
}
517+
(ins VR:$vs2, optype:$imm, VMaskCarryInOp:$vm),
518+
opcodestr, "$vd, $vs2, $imm, $vm">;
513519

514520
// op vd, vs2, imm, vm
515521
class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
@@ -1458,10 +1464,9 @@ defm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
14581464
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
14591465

14601466
// Vector Floating-Point Merge Instruction
1461-
let vm = 0 in
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def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
1463-
(ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
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"vfmerge.vfm", "$vd, $vs2, $rs1, v0">,
1468+
(ins VR:$vs2, FPR32:$rs1, VMaskCarryInOp:$vm),
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"vfmerge.vfm", "$vd, $vs2, $rs1, $vm">,
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SchedBinaryMC<"WriteVFMergeV", "ReadVFMergeV", "ReadVFMergeF">;
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14671472
// Vector Floating-Point Move Instruction

‎llvm/test/MC/Disassembler/RISCV/vmask-carry-in.txt‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
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# RUN: llvm-mc -triple=riscv64 -disassemble -show-inst --mattr=+v %s \
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# RUN: --M no-aliases | FileCheck %s
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# Check if there is a MCOperand for the carry-in mask.
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[0x57,0x04,0x4a,0x5c]
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# CHECK: <MCInst #{{[0-9]+}} VMERGE_VVM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0x44,0x45,0x5c]
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# CHECK: <MCInst #{{[0-9]+}} VMERGE_VXM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0xb4,0x47,0x5c]
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# CHECK: <MCInst #{{[0-9]+}} VMERGE_VIM
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Imm
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# CHECK-NEXT: MCOperand Reg
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[0x57,0x04,0x4a,0x40]
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# CHECK: <MCInst #{{[0-9]+}} VADC_VVM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0x44,0x45,0x40]
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# CHECK: <MCInst #{{[0-9]+}} VADC_VXM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0xb4,0x47,0x40]
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# CHECK: <MCInst #{{[0-9]+}} VADC_VIM
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Imm
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# CHECK-NEXT: MCOperand Reg
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[0x57,0x04,0x4a,0x44]
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# CHECK: <MCInst #{{[0-9]+}} VMADC_VVM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0x44,0x45,0x44]
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# CHECK: <MCInst #{{[0-9]+}} VMADC_VXM
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# CHECK-COUNT-4: MCOperand Reg
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44+
[0x57,0xb4,0x47,0x44]
45+
# CHECK: <MCInst #{{[0-9]+}} VMADC_VIM
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Imm
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# CHECK-NEXT: MCOperand Reg
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51+
[0x57,0x04,0x4a,0x48]
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# CHECK: <MCInst #{{[0-9]+}} VSBC_VVM
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# CHECK-COUNT-4: MCOperand Reg
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55+
[0x57,0x44,0x45,0x48]
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# CHECK: <MCInst #{{[0-9]+}} VSBC_VXM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0x04,0x4a,0x4c]
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# CHECK: <MCInst #{{[0-9]+}} VMSBC_VVM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0x44,0x45,0x4c]
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# CHECK: <MCInst #{{[0-9]+}} VMSBC_VXM
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# CHECK-COUNT-4: MCOperand Reg
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[0x57,0x54,0x45,0x5c]
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# CHECK: <MCInst #{{[0-9]+}} VFMERGE_VFM
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# CHECK-COUNT-4: MCOperand Reg

‎llvm/test/MC/RISCV/rvv/vmask-carry-in.s‎

Lines changed: 69 additions & 0 deletions
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@@ -0,0 +1,69 @@
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# RUN: llvm-mc -triple=riscv64 -show-inst --mattr=+v %s \
2+
# RUN: --M no-aliases | FileCheck %s
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4+
# Check if there is a MCOperand for the carry-in mask.
5+
6+
vmerge.vvm v8, v4, v20, v0
7+
# CHECK: <MCInst #{{[0-9]+}} VMERGE_VVM
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# CHECK-COUNT-4: MCOperand Reg
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vmerge.vxm v8, v4, a0, v0
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# CHECK: <MCInst #{{[0-9]+}} VMERGE_VXM
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# CHECK-COUNT-4: MCOperand Reg
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14+
vmerge.vim v8, v4, 15, v0
15+
# CHECK: <MCInst #{{[0-9]+}} VMERGE_VIM
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Imm
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# CHECK-NEXT: MCOperand Reg
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21+
vadc.vvm v8, v4, v20, v0
22+
# CHECK: <MCInst #{{[0-9]+}} VADC_VVM
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# CHECK-COUNT-4: MCOperand Reg
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vadc.vxm v8, v4, a0, v0
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# CHECK: <MCInst #{{[0-9]+}} VADC_VXM
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# CHECK-COUNT-4: MCOperand Reg
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29+
vadc.vim v8, v4, 15, v0
30+
# CHECK: <MCInst #{{[0-9]+}} VADC_VIM
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Reg
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# CHECK-NEXT: MCOperand Imm
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# CHECK-NEXT: MCOperand Reg
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36+
vmadc.vvm v8, v4, v20, v0
37+
# CHECK: <MCInst #{{[0-9]+}} VMADC_VVM
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# CHECK-COUNT-4: MCOperand Reg
39+
40+
vmadc.vxm v8, v4, a0, v0
41+
# CHECK: <MCInst #{{[0-9]+}} VMADC_VXM
42+
# CHECK-COUNT-4: MCOperand Reg
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44+
vmadc.vim v8, v4, 15, v0
45+
# CHECK: <MCInst #{{[0-9]+}} VMADC_VIM
46+
# CHECK-NEXT: MCOperand Reg
47+
# CHECK-NEXT: MCOperand Reg
48+
# CHECK-NEXT: MCOperand Imm
49+
# CHECK-NEXT: MCOperand Reg
50+
51+
vsbc.vvm v8, v4, v20, v0
52+
# CHECK: <MCInst #{{[0-9]+}} VSBC_VVM
53+
# CHECK-COUNT-4: MCOperand Reg
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55+
vsbc.vxm v8, v4, a0, v0
56+
# CHECK: <MCInst #{{[0-9]+}} VSBC_VXM
57+
# CHECK-COUNT-4: MCOperand Reg
58+
59+
vmsbc.vvm v8, v4, v20, v0
60+
# CHECK: <MCInst #{{[0-9]+}} VMSBC_VVM
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# CHECK-COUNT-4: MCOperand Reg
62+
63+
vmsbc.vxm v8, v4, a0, v0
64+
# CHECK: <MCInst #{{[0-9]+}} VMSBC_VXM
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# CHECK-COUNT-4: MCOperand Reg
66+
67+
vfmerge.vfm v8, v4, fa0, v0
68+
# CHECK: <MCInst #{{[0-9]+}} VFMERGE_VFM
69+
# CHECK-COUNT-4: MCOperand Reg

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