fix the comments

Author: LiqinWeng

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -17930,10 +17930,13 @@ AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
 
   SDValue ShiftLHS = N->getOperand(0);
   EVT VT = N->getValueType(0);
+  SDValue Add;
+
+  if (!ShiftLHS->hasOneUse())
+    return false;
 
   if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
-       !(ShiftLHS->hasOneUse() && ShiftLHS.getOperand(0)->hasOneUse())) ||
-      !ShiftLHS->hasOneUse())
+       !ShiftLHS.getOperand(0)->hasOneUse()))
     return false;
 
   // If ShiftLHS is unsigned bit extraction: ((x >> C) & mask), then do not
@@ -17954,6 +17957,7 @@ AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
       }
     }
   }
+
   return true;
 }
 

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -1074,9 +1074,11 @@ bool AMDGPUTargetLowering::isDesirableToCommuteWithShift(
          "Expected shift op");
 
   SDValue ShiftLHS = N->getOperand(0);
+  if (!ShiftLHS->hasOneUse())
+    return false;
+
   if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
-       !(ShiftLHS->hasOneUse() && ShiftLHS.getOperand(0)->hasOneUse())) ||
-      !ShiftLHS->hasOneUse())
+       !ShiftLHS.getOperand(0)->hasOneUse()))
     return false;
 
   // Always commute pre-type legalization and right shifts.

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -13881,9 +13881,11 @@ ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
          "Expected shift op");
 
   SDValue ShiftLHS = N->getOperand(0);
+  if (!ShiftLHS->hasOneUse())
+    return false;
+
   if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
-       !(ShiftLHS->hasOneUse() && ShiftLHS.getOperand(0)->hasOneUse())) ||
-      !ShiftLHS->hasOneUse())
+       !ShiftLHS.getOperand(0)->hasOneUse()))
     return false;
 
   if (Level == BeforeLegalizeTypes)

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

@@ -2154,17 +2154,19 @@ bool HexagonTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
 
 bool HexagonTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
+  using namespace llvm::SDPatternMatch;
   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
           N->getOpcode() == ISD::SRL) &&
          "Expected shift op");
 
   SDValue ShiftLHS = N->getOperand(0);
-  if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
-       !(ShiftLHS->hasOneUse() && ShiftLHS.getOperand(0)->hasOneUse())) ||
-      !ShiftLHS->hasOneUse())
-    return false;
+  SDValue Add;
 
-  return true;
+  if (ShiftLHS->hasOneUse() ||
+      sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))))
+    return true;
+
+  return false;
 }
 
 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -19169,15 +19169,17 @@ Value *PPCTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
 
 bool PPCTargetLowering::isDesirableToCommuteWithShift(
     const SDNode *N, CombineLevel Level) const {
+  using namespace llvm::SDPatternMatch;
   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
           N->getOpcode() == ISD::SRL) &&
          "Expected shift op");
 
   SDValue ShiftLHS = N->getOperand(0);
-  if ((ShiftLHS.getOpcode() == ISD::SIGN_EXTEND &&
-       !(ShiftLHS->hasOneUse() && ShiftLHS.getOperand(0)->hasOneUse())) ||
-      !ShiftLHS->hasOneUse())
-    return false;
+  SDValue Add;
 
-  return true;
+  if (ShiftLHS->hasOneUse() ||
+      sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))))
+    return true;
+
+  return false;
 }

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -60683,8 +60683,9 @@ bool X86TargetLowering::isDesirableToCommuteWithShift(
 
   SDValue ShiftLHS = N->getOperand(0);
   SDValue Add;
-  if (sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))) ||
-      ShiftLHS->hasOneUse())
+
+  if (ShiftLHS->hasOneUse() ||
+      sd_match(ShiftLHS, m_OneUse(m_SExt(m_OneUse(m_Value(Add))))))
     return true;
 
   return false;