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[RISCV] Fix variable naming in recently pre-committed test
I'd swapped the %add/%sub names, and then copied that repeatedly. Oops. While updating, remove the nsw as those should be irrelevant and is another copy-paste mistake on my part.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,9 @@ define <1 x i32> @select_addsub_v1i32(<1 x i1> %cc, <1 x i32> %a, <1 x i32> %b)
1313
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
1414
; CHECK-NEXT: vmv1r.v v8, v10
1515
; CHECK-NEXT: ret
16-
%add = sub nsw <1 x i32> %a, %b
17-
%sub = add nsw <1 x i32> %a, %b
18-
%res = select <1 x i1> %cc, <1 x i32> %add, <1 x i32> %sub
16+
%sub = sub <1 x i32> %a, %b
17+
%add = add <1 x i32> %a, %b
18+
%res = select <1 x i1> %cc, <1 x i32> %sub, <1 x i32> %add
1919
ret <1 x i32> %res
2020
}
2121

@@ -27,9 +27,9 @@ define <2 x i32> @select_addsub_v2i32(<2 x i1> %cc, <2 x i32> %a, <2 x i32> %b)
2727
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
2828
; CHECK-NEXT: vmv1r.v v8, v10
2929
; CHECK-NEXT: ret
30-
%add = sub nsw <2 x i32> %a, %b
31-
%sub = add nsw <2 x i32> %a, %b
32-
%res = select <2 x i1> %cc, <2 x i32> %add, <2 x i32> %sub
30+
%sub = sub <2 x i32> %a, %b
31+
%add = add <2 x i32> %a, %b
32+
%res = select <2 x i1> %cc, <2 x i32> %sub, <2 x i32> %add
3333
ret <2 x i32> %res
3434
}
3535

@@ -41,9 +41,9 @@ define <4 x i32> @select_addsub_v4i32(<4 x i1> %cc, <4 x i32> %a, <4 x i32> %b)
4141
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
4242
; CHECK-NEXT: vmv.v.v v8, v10
4343
; CHECK-NEXT: ret
44-
%add = sub nsw <4 x i32> %a, %b
45-
%sub = add nsw <4 x i32> %a, %b
46-
%res = select <4 x i1> %cc, <4 x i32> %add, <4 x i32> %sub
44+
%sub = sub <4 x i32> %a, %b
45+
%add = add <4 x i32> %a, %b
46+
%res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add
4747
ret <4 x i32> %res
4848
}
4949

@@ -55,9 +55,9 @@ define <4 x i32> @select_addsub_v4i32_select_swapped(<4 x i1> %cc, <4 x i32> %a,
5555
; CHECK-NEXT: vadd.vv v10, v8, v9, v0.t
5656
; CHECK-NEXT: vmv.v.v v8, v10
5757
; CHECK-NEXT: ret
58-
%add = sub nsw <4 x i32> %a, %b
59-
%sub = add nsw <4 x i32> %a, %b
60-
%res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add
58+
%sub = sub <4 x i32> %a, %b
59+
%add = add <4 x i32> %a, %b
60+
%res = select <4 x i1> %cc, <4 x i32> %add, <4 x i32> %sub
6161
ret <4 x i32> %res
6262
}
6363

@@ -69,9 +69,9 @@ define <4 x i32> @select_addsub_v4i32_add_swapped(<4 x i1> %cc, <4 x i32> %a, <4
6969
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
7070
; CHECK-NEXT: vmv.v.v v8, v10
7171
; CHECK-NEXT: ret
72-
%add = sub nsw <4 x i32> %a, %b
73-
%sub = add nsw <4 x i32> %b, %a
74-
%res = select <4 x i1> %cc, <4 x i32> %add, <4 x i32> %sub
72+
%sub = sub <4 x i32> %a, %b
73+
%add = add <4 x i32> %b, %a
74+
%res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add
7575
ret <4 x i32> %res
7676
}
7777

@@ -83,9 +83,9 @@ define <4 x i32> @select_addsub_v4i32_both_swapped(<4 x i1> %cc, <4 x i32> %a, <
8383
; CHECK-NEXT: vadd.vv v10, v9, v8, v0.t
8484
; CHECK-NEXT: vmv.v.v v8, v10
8585
; CHECK-NEXT: ret
86-
%add = sub nsw <4 x i32> %a, %b
87-
%sub = add nsw <4 x i32> %b, %a
88-
%res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add
86+
%sub = sub <4 x i32> %a, %b
87+
%add = add <4 x i32> %b, %a
88+
%res = select <4 x i1> %cc, <4 x i32> %add, <4 x i32> %sub
8989
ret <4 x i32> %res
9090
}
9191

@@ -97,9 +97,9 @@ define <4 x i32> @select_addsub_v4i32_sub_swapped(<4 x i1> %cc, <4 x i32> %a, <4
9797
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
9898
; CHECK-NEXT: vmv.v.v v8, v10
9999
; CHECK-NEXT: ret
100-
%add = sub nsw <4 x i32> %a, %b
101-
%sub = add nsw <4 x i32> %b, %a
102-
%res = select <4 x i1> %cc, <4 x i32> %add, <4 x i32> %sub
100+
%sub = sub <4 x i32> %a, %b
101+
%add = add <4 x i32> %b, %a
102+
%res = select <4 x i1> %cc, <4 x i32> %sub, <4 x i32> %add
103103
ret <4 x i32> %res
104104
}
105105

@@ -111,9 +111,9 @@ define <8 x i32> @select_addsub_v8i32(<8 x i1> %cc, <8 x i32> %a, <8 x i32> %b)
111111
; CHECK-NEXT: vsub.vv v12, v8, v10, v0.t
112112
; CHECK-NEXT: vmv.v.v v8, v12
113113
; CHECK-NEXT: ret
114-
%add = sub nsw <8 x i32> %a, %b
115-
%sub = add nsw <8 x i32> %a, %b
116-
%res = select <8 x i1> %cc, <8 x i32> %add, <8 x i32> %sub
114+
%sub = sub <8 x i32> %a, %b
115+
%add = add <8 x i32> %a, %b
116+
%res = select <8 x i1> %cc, <8 x i32> %sub, <8 x i32> %add
117117
ret <8 x i32> %res
118118
}
119119

@@ -125,9 +125,9 @@ define <16 x i32> @select_addsub_v16i32(<16 x i1> %cc, <16 x i32> %a, <16 x i32>
125125
; CHECK-NEXT: vsub.vv v16, v8, v12, v0.t
126126
; CHECK-NEXT: vmv.v.v v8, v16
127127
; CHECK-NEXT: ret
128-
%add = sub nsw <16 x i32> %a, %b
129-
%sub = add nsw <16 x i32> %a, %b
130-
%res = select <16 x i1> %cc, <16 x i32> %add, <16 x i32> %sub
128+
%sub = sub <16 x i32> %a, %b
129+
%add = add <16 x i32> %a, %b
130+
%res = select <16 x i1> %cc, <16 x i32> %sub, <16 x i32> %add
131131
ret <16 x i32> %res
132132
}
133133

@@ -140,9 +140,9 @@ define <32 x i32> @select_addsub_v32i32(<32 x i1> %cc, <32 x i32> %a, <32 x i32>
140140
; CHECK-NEXT: vsub.vv v24, v8, v16, v0.t
141141
; CHECK-NEXT: vmv.v.v v8, v24
142142
; CHECK-NEXT: ret
143-
%add = sub nsw <32 x i32> %a, %b
144-
%sub = add nsw <32 x i32> %a, %b
145-
%res = select <32 x i1> %cc, <32 x i32> %add, <32 x i32> %sub
143+
%sub = sub <32 x i32> %a, %b
144+
%add = add <32 x i32> %a, %b
145+
%res = select <32 x i1> %cc, <32 x i32> %sub, <32 x i32> %add
146146
ret <32 x i32> %res
147147
}
148148

@@ -214,9 +214,9 @@ define <64 x i32> @select_addsub_v64i32(<64 x i1> %cc, <64 x i32> %a, <64 x i32>
214214
; CHECK-NEXT: addi sp, sp, 16
215215
; CHECK-NEXT: .cfi_def_cfa_offset 0
216216
; CHECK-NEXT: ret
217-
%add = sub nsw <64 x i32> %a, %b
218-
%sub = add nsw <64 x i32> %a, %b
219-
%res = select <64 x i1> %cc, <64 x i32> %add, <64 x i32> %sub
217+
%sub = sub <64 x i32> %a, %b
218+
%add = add <64 x i32> %a, %b
219+
%res = select <64 x i1> %cc, <64 x i32> %sub, <64 x i32> %add
220220
ret <64 x i32> %res
221221
}
222222

@@ -228,9 +228,9 @@ define <8 x i64> @select_addsub_v8i64(<8 x i1> %cc, <8 x i64> %a, <8 x i64> %b)
228228
; CHECK-NEXT: vsub.vv v16, v8, v12, v0.t
229229
; CHECK-NEXT: vmv.v.v v8, v16
230230
; CHECK-NEXT: ret
231-
%add = sub nsw <8 x i64> %a, %b
232-
%sub = add nsw <8 x i64> %a, %b
233-
%res = select <8 x i1> %cc, <8 x i64> %add, <8 x i64> %sub
231+
%sub = sub <8 x i64> %a, %b
232+
%add = add <8 x i64> %a, %b
233+
%res = select <8 x i1> %cc, <8 x i64> %sub, <8 x i64> %add
234234
ret <8 x i64> %res
235235
}
236236

@@ -242,9 +242,9 @@ define <8 x i16> @select_addsub_v8i16(<8 x i1> %cc, <8 x i16> %a, <8 x i16> %b)
242242
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
243243
; CHECK-NEXT: vmv.v.v v8, v10
244244
; CHECK-NEXT: ret
245-
%add = sub nsw <8 x i16> %a, %b
246-
%sub = add nsw <8 x i16> %a, %b
247-
%res = select <8 x i1> %cc, <8 x i16> %add, <8 x i16> %sub
245+
%sub = sub <8 x i16> %a, %b
246+
%add = add <8 x i16> %a, %b
247+
%res = select <8 x i1> %cc, <8 x i16> %sub, <8 x i16> %add
248248
ret <8 x i16> %res
249249
}
250250

@@ -256,9 +256,9 @@ define <8 x i8> @select_addsub_v8i8(<8 x i1> %cc, <8 x i8> %a, <8 x i8> %b) {
256256
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
257257
; CHECK-NEXT: vmv1r.v v8, v10
258258
; CHECK-NEXT: ret
259-
%add = sub nsw <8 x i8> %a, %b
260-
%sub = add nsw <8 x i8> %a, %b
261-
%res = select <8 x i1> %cc, <8 x i8> %add, <8 x i8> %sub
259+
%sub = sub <8 x i8> %a, %b
260+
%add = add <8 x i8> %a, %b
261+
%res = select <8 x i1> %cc, <8 x i8> %sub, <8 x i8> %add
262262
ret <8 x i8> %res
263263
}
264264

@@ -268,9 +268,9 @@ define <8 x i1> @select_addsub_v8i1(<8 x i1> %cc, <8 x i1> %a, <8 x i1> %b) {
268268
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
269269
; CHECK-NEXT: vmxor.mm v0, v8, v9
270270
; CHECK-NEXT: ret
271-
%add = sub nsw <8 x i1> %a, %b
272-
%sub = add nsw <8 x i1> %a, %b
273-
%res = select <8 x i1> %cc, <8 x i1> %add, <8 x i1> %sub
271+
%sub = sub <8 x i1> %a, %b
272+
%add = add <8 x i1> %a, %b
273+
%res = select <8 x i1> %cc, <8 x i1> %sub, <8 x i1> %add
274274
ret <8 x i1> %res
275275
}
276276

@@ -282,9 +282,9 @@ define <8 x i2> @select_addsub_v8i2(<8 x i1> %cc, <8 x i2> %a, <8 x i2> %b) {
282282
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
283283
; CHECK-NEXT: vmv1r.v v8, v10
284284
; CHECK-NEXT: ret
285-
%add = sub nsw <8 x i2> %a, %b
286-
%sub = add nsw <8 x i2> %a, %b
287-
%res = select <8 x i1> %cc, <8 x i2> %add, <8 x i2> %sub
285+
%sub = sub <8 x i2> %a, %b
286+
%add = add <8 x i2> %a, %b
287+
%res = select <8 x i1> %cc, <8 x i2> %sub, <8 x i2> %add
288288
ret <8 x i2> %res
289289
}
290290

@@ -297,9 +297,9 @@ define <4 x i32> @select_addsub_v4i32_constmask(<4 x i32> %a, <4 x i32> %b) {
297297
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
298298
; CHECK-NEXT: vmv.v.v v8, v10
299299
; CHECK-NEXT: ret
300-
%add = sub nsw <4 x i32> %a, %b
301-
%sub = add nsw <4 x i32> %a, %b
302-
%res = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %add, <4 x i32> %sub
300+
%sub = sub <4 x i32> %a, %b
301+
%add = add <4 x i32> %a, %b
302+
%res = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %sub, <4 x i32> %add
303303
ret <4 x i32> %res
304304
}
305305

@@ -312,9 +312,9 @@ define <4 x i32> @select_addsub_v4i32_constmask2(<4 x i32> %a, <4 x i32> %b) {
312312
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
313313
; CHECK-NEXT: vmv.v.v v8, v10
314314
; CHECK-NEXT: ret
315-
%add = sub nsw <4 x i32> %a, %b
316-
%sub = add nsw <4 x i32> %b, %a
317-
%res = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %add, <4 x i32> %sub
315+
%sub = sub <4 x i32> %a, %b
316+
%add = add <4 x i32> %b, %a
317+
%res = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %sub, <4 x i32> %add
318318
ret <4 x i32> %res
319319
}
320320

@@ -328,9 +328,9 @@ define <4 x i32> @select_addsub_v4i32_as_shuffle(<4 x i32> %a, <4 x i32> %b) {
328328
; CHECK-NEXT: vsub.vv v10, v8, v9, v0.t
329329
; CHECK-NEXT: vmv.v.v v8, v10
330330
; CHECK-NEXT: ret
331-
%add = sub nsw <4 x i32> %a, %b
332-
%sub = add nsw <4 x i32> %a, %b
333-
%res = shufflevector <4 x i32> %add, <4 x i32> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
331+
%sub = sub <4 x i32> %a, %b
332+
%add = add <4 x i32> %a, %b
333+
%res = shufflevector <4 x i32> %sub, <4 x i32> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
334334
ret <4 x i32> %res
335335
}
336336

@@ -344,8 +344,8 @@ define <4 x i32> @select_addsub_v4i32_as_shuffle2(<4 x i32> %a, <4 x i32> %b) {
344344
; CHECK-NEXT: vsub.vv v10, v9, v8, v0.t
345345
; CHECK-NEXT: vmv.v.v v8, v10
346346
; CHECK-NEXT: ret
347-
%add = sub nsw <4 x i32> %b, %a
348-
%sub = add nsw <4 x i32> %a, %b
349-
%res = shufflevector <4 x i32> %add, <4 x i32> %sub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
347+
%sub = sub <4 x i32> %b, %a
348+
%add = add <4 x i32> %a, %b
349+
%res = shufflevector <4 x i32> %sub, <4 x i32> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
350350
ret <4 x i32> %res
351351
}

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