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topperctopperc
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[Mips] Remove implicit conversions of MCRegister to unsigned. NFC (#167645)
1 parent 7d5c11f commit 0845c5a

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6 files changed

+184
-183
lines changed

6 files changed

+184
-183
lines changed

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp‎

Lines changed: 40 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ class MipsAsmParser : public MCTargetAsmParser {
151151
bool IsCpRestoreSet;
152152
bool CurForbiddenSlotAttr;
153153
int CpRestoreOffset;
154-
unsigned GPReg;
154+
MCRegister GPReg;
155155
unsigned CpSaveLocation;
156156
/// If true, then CpSaveLocation is a register, otherwise it's an offset.
157157
bool CpSaveLocationIsRegister;
@@ -823,7 +823,7 @@ class MipsOperand : public MCParsedAsmOperand {
823823
};
824824

825825
struct RegListOp {
826-
SmallVector<unsigned, 10> *List;
826+
SmallVector<MCRegister, 10> *List;
827827
};
828828

829829
union {
@@ -1377,15 +1377,15 @@ class MipsOperand : public MCParsedAsmOperand {
13771377
if (Size < 2 || Size > 5)
13781378
return false;
13791379

1380-
unsigned R0 = RegList.List->front();
1381-
unsigned R1 = RegList.List->back();
1380+
MCRegister R0 = RegList.List->front();
1381+
MCRegister R1 = RegList.List->back();
13821382
if (!((R0 == Mips::S0 && R1 == Mips::RA) ||
13831383
(R0 == Mips::S0_64 && R1 == Mips::RA_64)))
13841384
return false;
13851385

1386-
int PrevReg = *RegList.List->begin();
1386+
MCRegister PrevReg = RegList.List->front();
13871387
for (int i = 1; i < Size - 1; i++) {
1388-
int Reg = (*(RegList.List))[i];
1388+
MCRegister Reg = (*(RegList.List))[i];
13891389
if ( Reg != PrevReg + 1)
13901390
return false;
13911391
PrevReg = Reg;
@@ -1447,7 +1447,7 @@ class MipsOperand : public MCParsedAsmOperand {
14471447
return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
14481448
}
14491449

1450-
const SmallVectorImpl<unsigned> &getRegList() const {
1450+
const SmallVectorImpl<MCRegister> &getRegList() const {
14511451
assert((Kind == k_RegList) && "Invalid access!");
14521452
return *(RegList.List);
14531453
}
@@ -1548,12 +1548,13 @@ class MipsOperand : public MCParsedAsmOperand {
15481548
}
15491549

15501550
static std::unique_ptr<MipsOperand>
1551-
CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc,
1551+
CreateRegList(SmallVectorImpl<MCRegister> &Regs, SMLoc StartLoc, SMLoc EndLoc,
15521552
MipsAsmParser &Parser) {
1553-
assert(Regs.size() > 0 && "Empty list not allowed");
1553+
assert(!Regs.empty() && "Empty list not allowed");
15541554

15551555
auto Op = std::make_unique<MipsOperand>(k_RegList, Parser);
1556-
Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end());
1556+
Op->RegList.List =
1557+
new SmallVector<MCRegister, 10>(Regs.begin(), Regs.end());
15571558
Op->StartLoc = StartLoc;
15581559
Op->EndLoc = EndLoc;
15591560
return Op;
@@ -1684,7 +1685,7 @@ class MipsOperand : public MCParsedAsmOperand {
16841685
case k_RegList:
16851686
OS << "RegList< ";
16861687
for (auto Reg : (*RegList.List))
1687-
OS << Reg << " ";
1688+
OS << Reg.id() << " ";
16881689
OS << ">";
16891690
break;
16901691
}
@@ -6848,9 +6849,9 @@ ParseStatus MipsAsmParser::parseInvNum(OperandVector &Operands) {
68486849

68496850
ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) {
68506851
MCAsmParser &Parser = getParser();
6851-
SmallVector<unsigned, 10> Regs;
6852-
unsigned RegNo;
6853-
unsigned PrevReg = Mips::NoRegister;
6852+
SmallVector<MCRegister, 10> Regs;
6853+
MCRegister Reg;
6854+
MCRegister PrevReg;
68546855
bool RegRange = false;
68556856
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands;
68566857

@@ -6860,46 +6861,47 @@ ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) {
68606861
SMLoc S = Parser.getTok().getLoc();
68616862
while (parseAnyRegister(TmpOperands).isSuccess()) {
68626863
SMLoc E = getLexer().getLoc();
6863-
MipsOperand &Reg = static_cast<MipsOperand &>(*TmpOperands.back());
6864-
RegNo = isGP64bit() ? Reg.getGPR64Reg() : Reg.getGPR32Reg();
6864+
MipsOperand &RegOpnd = static_cast<MipsOperand &>(*TmpOperands.back());
6865+
Reg = isGP64bit() ? RegOpnd.getGPR64Reg() : RegOpnd.getGPR32Reg();
68656866
if (RegRange) {
68666867
// Remove last register operand because registers from register range
68676868
// should be inserted first.
6868-
if ((isGP64bit() && RegNo == Mips::RA_64) ||
6869-
(!isGP64bit() && RegNo == Mips::RA)) {
6870-
Regs.push_back(RegNo);
6869+
if ((isGP64bit() && Reg == Mips::RA_64) ||
6870+
(!isGP64bit() && Reg == Mips::RA)) {
6871+
Regs.push_back(Reg);
68716872
} else {
6872-
unsigned TmpReg = PrevReg + 1;
6873-
while (TmpReg <= RegNo) {
6873+
MCRegister TmpReg = PrevReg + 1;
6874+
while (TmpReg <= Reg) {
68746875
if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) ||
68756876
(((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) &&
68766877
isGP64bit()))
68776878
return Error(E, "invalid register operand");
68786879

68796880
PrevReg = TmpReg;
6880-
Regs.push_back(TmpReg++);
6881+
Regs.push_back(TmpReg);
6882+
TmpReg = TmpReg.id() + 1;
68816883
}
68826884
}
68836885

68846886
RegRange = false;
68856887
} else {
6886-
if ((PrevReg == Mips::NoRegister) &&
6887-
((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) ||
6888-
(!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA))))
6888+
if (!PrevReg.isValid() &&
6889+
((isGP64bit() && (Reg != Mips::S0_64) && (Reg != Mips::RA_64)) ||
6890+
(!isGP64bit() && (Reg != Mips::S0) && (Reg != Mips::RA))))
68896891
return Error(E, "$16 or $31 expected");
6890-
if (!(((RegNo == Mips::FP || RegNo == Mips::RA ||
6891-
(RegNo >= Mips::S0 && RegNo <= Mips::S7)) &&
6892+
if (!(((Reg == Mips::FP || Reg == Mips::RA ||
6893+
(Reg >= Mips::S0 && Reg <= Mips::S7)) &&
68926894
!isGP64bit()) ||
6893-
((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 ||
6894-
(RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) &&
6895+
((Reg == Mips::FP_64 || Reg == Mips::RA_64 ||
6896+
(Reg >= Mips::S0_64 && Reg <= Mips::S7_64)) &&
68956897
isGP64bit())))
68966898
return Error(E, "invalid register operand");
6897-
if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) &&
6898-
((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) ||
6899-
(RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && isGP64bit())))
6899+
if (PrevReg.isValid() && (Reg != PrevReg + 1) &&
6900+
((Reg != Mips::FP && Reg != Mips::RA && !isGP64bit()) ||
6901+
(Reg != Mips::FP_64 && Reg != Mips::RA_64 && isGP64bit())))
69006902
return Error(E, "consecutive register numbers expected");
69016903

6902-
Regs.push_back(RegNo);
6904+
Regs.push_back(Reg);
69036905
}
69046906

69056907
if (Parser.getTok().is(AsmToken::Minus))
@@ -6913,7 +6915,7 @@ ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) {
69136915
if (Parser.getTok().isNot(AsmToken::Dollar))
69146916
break;
69156917

6916-
PrevReg = RegNo;
6918+
PrevReg = Reg;
69176919
}
69186920

69196921
SMLoc E = Parser.getTok().getLoc();
@@ -7780,7 +7782,7 @@ bool MipsAsmParser::parseDirectiveCpLocal(SMLoc Loc) {
77807782
}
77817783
getParser().Lex(); // Consume the EndOfStatement.
77827784

7783-
unsigned NewReg = RegOpnd.getGPR32Reg();
7785+
MCRegister NewReg = RegOpnd.getGPR32Reg();
77847786
if (IsPicEnabled)
77857787
GPReg = NewReg;
77867788

@@ -7835,7 +7837,6 @@ bool MipsAsmParser::parseDirectiveCpRestore(SMLoc Loc) {
78357837

78367838
bool MipsAsmParser::parseDirectiveCPSetup() {
78377839
MCAsmParser &Parser = getParser();
7838-
unsigned FuncReg;
78397840
unsigned Save;
78407841
bool SaveIsReg = true;
78417842

@@ -7852,7 +7853,7 @@ bool MipsAsmParser::parseDirectiveCPSetup() {
78527853
return false;
78537854
}
78547855

7855-
FuncReg = FuncRegOpnd.getGPR32Reg();
7856+
MCRegister FuncReg = FuncRegOpnd.getGPR32Reg();
78567857
TmpReg.clear();
78577858

78587859
if (!eatComma("unexpected token, expected comma"))
@@ -7878,7 +7879,7 @@ bool MipsAsmParser::parseDirectiveCPSetup() {
78787879
reportParseError(SaveOpnd.getStartLoc(), "invalid register");
78797880
return false;
78807881
}
7881-
Save = SaveOpnd.getGPR32Reg();
7882+
Save = SaveOpnd.getGPR32Reg().id();
78827883
}
78837884

78847885
if (!eatComma("unexpected token, expected comma"))
@@ -8696,7 +8697,7 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
86968697
"expected general purpose register");
86978698
return false;
86988699
}
8699-
unsigned StackReg = StackRegOpnd.getGPR32Reg();
8700+
MCRegister StackReg = StackRegOpnd.getGPR32Reg();
87008701

87018702
if (Parser.getTok().is(AsmToken::Comma))
87028703
Parser.Lex();

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