[RISCV] Create disjoint or in RISCVGatherScatterLowering (#151981)

We can create disjoint or in IRBuilder since #146350.

---------

Co-authored-by: Min-Yih Hsu <[email protected]>

Author: el-ev

llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp

@@ -167,9 +167,8 @@ static std::pair<Value *, Value *> matchStridedStart(Value *Start,
   default:
     llvm_unreachable("Unexpected opcode");
   case Instruction::Or:
-    // TODO: We'd be better off creating disjoint or here, but we don't yet
-    // have an IRBuilder API for that.
-    [[fallthrough]];
+    Start = Builder.CreateOr(Start, Splat, "", /*IsDisjoint=*/true);
+    break;
   case Instruction::Add:
     Start = Builder.CreateAdd(Start, Splat);
     break;

llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll

@@ -467,7 +467,7 @@ define <vscale x 1 x i64> @straightline_offset_disjoint_or_1(ptr %p) {
 define <vscale x 1 x i64> @straightline_offset_disjoint_or(ptr %p, i1 %offset) {
 ; CHECK-LABEL: @straightline_offset_disjoint_or(
 ; CHECK-NEXT:    [[AND:%.*]] = zext i1 [[OFFSET:%.*]] to i64
-; CHECK-NEXT:    [[TMP4:%.*]] = add i64 4, [[AND]]
+; CHECK-NEXT:    [[TMP4:%.*]] = or disjoint i64 4, [[AND]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP4]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vscale.i32()
 ; CHECK-NEXT:    [[TMP3:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64.p0.i64(ptr [[TMP1]], i64 8, <vscale x 1 x i1> splat (i1 true), i32 [[TMP2]])