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Invoke the SPIRV backend directly and add -ccc-print-phases and -ccc-print-bindings test cases.
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7 files changed

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‎clang/include/clang/Driver/Types.def‎

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Original file line numberDiff line numberDiff line change
@@ -78,6 +78,7 @@ TYPE("c++-module-cpp-output", PP_CXXModule, INVALID, "iim", phases
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TYPE("ada", Ada, INVALID, nullptr, phases::Compile, phases::Backend, phases::Assemble, phases::Link)
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TYPE("assembler", PP_Asm, INVALID, "s", phases::Assemble, phases::Link)
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TYPE("assembler-with-cpp", Asm, PP_Asm, "S", phases::Preprocess, phases::Assemble, phases::Link)
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TYPE("spv", SPV, INVALID, "spv", phases::Backend)
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// Note: The `phases::Preprocess` phase is added to ".i" (i.e. Fortran
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// pre-processed) files. The reason is that the pre-processor "phase" has to be

‎clang/lib/Driver/Driver.cpp‎

Lines changed: 28 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3672,29 +3672,45 @@ class OffloadingActionBuilder final {
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// compiler phases, including backend and assemble phases.
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ActionList AL;
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Action *BackendAction = nullptr;
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bool AssembleAndLink = true;
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if (ToolChains.front()->getTriple().isSPIRV() ||
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(ToolChains.front()->getTriple().isAMDGCN() &&
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GpuArchList[I] == StringRef("amdgcnspirv"))) {
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// Emit LLVM bitcode for SPIR-V targets. SPIR-V device tool chain
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// (HIPSPVToolChain or HIPAMDToolChain) runs post-link LLVM IR
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// passes.
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types::ID Output = Args.hasArg(options::OPT_S)
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bool UseSPIRVBackend =
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Args.hasFlag(options::OPT_use_experimental_spirv_backend,
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options::OPT_no_use_experimental_spirv_backend,
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/*Default=*/false);
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types::ID Output = UseSPIRVBackend ? types::TY_SPV
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: Args.hasArg(options::OPT_S)
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? types::TY_LLVM_IR
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: types::TY_LLVM_BC;
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BackendAction =
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C.MakeAction<BackendJobAction>(CudaDeviceActions[I], Output);
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3693+
if (UseSPIRVBackend) {
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AssembleAndLink = false;
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}
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} else
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BackendAction = C.getDriver().ConstructPhaseAction(
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C, Args, phases::Backend, CudaDeviceActions[I],
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AssociatedOffloadKind);
3690-
auto AssembleAction = C.getDriver().ConstructPhaseAction(
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C, Args, phases::Assemble, BackendAction,
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AssociatedOffloadKind);
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AL.push_back(AssembleAction);
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// Create a link action to link device IR with device library
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// and generate ISA.
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CudaDeviceActions[I] =
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C.MakeAction<LinkJobAction>(AL, types::TY_Image);
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3702+
if (AssembleAndLink) {
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auto AssembleAction = C.getDriver().ConstructPhaseAction(
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C, Args, phases::Assemble, BackendAction,
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AssociatedOffloadKind);
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AL.push_back(AssembleAction);
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// Create a link action to link device IR with device library
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// and generate ISA.
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CudaDeviceActions[I] =
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C.MakeAction<LinkJobAction>(AL, types::TY_Image);
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} else {
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CudaDeviceActions[I] = BackendAction;
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}
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}
36993715

37003716
// OffloadingActionBuilder propagates device arch until an offload

‎clang/lib/Driver/ToolChains/Clang.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5197,6 +5197,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
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rewriteKind = RK_Fragile;
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} else if (JA.getType() == types::TY_CIR) {
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CmdArgs.push_back("-emit-cir");
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} else if (JA.getType() == types::TY_SPV) {
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CmdArgs.push_back("-emit-obj");
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} else {
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assert(JA.getType() == types::TY_PP_Asm && "Unexpected output type!");
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}

‎clang/lib/Driver/ToolChains/HIPAMD.cpp‎

Lines changed: 9 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -175,33 +175,15 @@ void AMDGCN::Linker::constructLinkAndEmitSpirvCommand(
175175

176176
constructLlvmLinkCommand(C, JA, Inputs, LinkedBCFile, Args);
177177

178-
bool UseSPIRVBackend = Args.hasFlag(
179-
options::OPT_use_experimental_spirv_backend,
180-
options::OPT_no_use_experimental_spirv_backend, /*Default=*/false);
181-
182-
// Emit SPIR-V binary either using the SPIRV backend or the translator.
183-
if (UseSPIRVBackend) {
184-
llvm::opt::ArgStringList CmdArgs;
185-
const char *Triple =
186-
C.getArgs().MakeArgString("-triple=spirv64-amd-amdhsa");
187-
CmdArgs.append({"-cc1", Triple, "-emit-obj", LinkedBCFile.getFilename(),
188-
"-o", Output.getFilename()});
189-
const char *Exec = getToolChain().getDriver().getClangProgramPath();
190-
C.addCommand(std::make_unique<Command>(JA, *this,
191-
ResponseFileSupport::None(), Exec,
192-
CmdArgs, LinkedBCFile, Output));
193-
} else {
194-
// Use the SPIRV translator for code gen.
195-
llvm::opt::ArgStringList TrArgs{
196-
"--spirv-max-version=1.6",
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"--spirv-ext=+all",
198-
"--spirv-allow-unknown-intrinsics",
199-
"--spirv-lower-const-expr",
200-
"--spirv-preserve-auxdata",
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"--spirv-debug-info-version=nonsemantic-shader-200"};
202-
SPIRV::constructTranslateCommand(C, *this, JA, Output, LinkedBCFile,
203-
TrArgs);
204-
}
178+
// Use the SPIRV translator for code gen.
179+
llvm::opt::ArgStringList TrArgs{
180+
"--spirv-max-version=1.6",
181+
"--spirv-ext=+all",
182+
"--spirv-allow-unknown-intrinsics",
183+
"--spirv-lower-const-expr",
184+
"--spirv-preserve-auxdata",
185+
"--spirv-debug-info-version=nonsemantic-shader-200"};
186+
SPIRV::constructTranslateCommand(C, *this, JA, Output, LinkedBCFile, TrArgs);
205187
}
206188

207189
// For amdgcn the inputs of the linker job are device bitcode and output is

‎clang/test/Driver/hip-spirv-backend-bindings.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
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// RUN: %clang -x hip %s --cuda-device-only --offload-arch=amdgcnspirv -use-experimental-spirv-backend -nogpuinc -nogpulib -ccc-print-bindings 2>&1 | FileCheck %s
2+
3+
// CHECK: # "spirv64-amd-amdhsa" - "clang", inputs: ["{{.*}}.c"], output: "[[SPV_FILE:.*.spv]]"
4+
// CHECK: # "spirv64-amd-amdhsa" - "AMDGCN::Linker", inputs: ["[[SPV_FILE]]"], output: "{{.*.hipfb}}"

‎clang/test/Driver/hip-spirv-backend-opt.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

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// Test that -use-experimental-spirv-backend calls clang -cc1 with the SPIRV triple.
44
// RUN: %clang -x hip %s --cuda-device-only --offload-arch=amdgcnspirv -use-experimental-spirv-backend -nogpuinc -nogpulib -### 2>&1 | FileCheck %s --check-prefix=CHECK-SPIRV-BACKEND
5-
// CHECK-SPIRV-BACKEND: "{{.*}}clang{{.*}}" "-cc1" "{{.*-triple=spirv64-amd-amdhsa}}"
5+
// CHECK-SPIRV-BACKEND: "{{.*}}clang{{.*}}" "-cc1" "{{.*-triple}}" "{{spirv64-amd-amdhsa}}"
66

77
// Test that -no-use-experimental-spirv-backend calls the SPIRV translator
88
// RUN: %clang -x hip %s --cuda-device-only --offload-arch=amdgcnspirv -no-use-experimental-spirv-backend -nogpuinc -nogpulib -### 2>&1 | FileCheck %s --check-prefix=CHECK-SPIRV-TRANSLATOR

‎clang/test/Driver/hip-spirv-backend-phases.c‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
// RUN: %clang -x hip %s --cuda-device-only --offload-arch=amdgcnspirv -use-experimental-spirv-backend -nogpuinc -nogpulib -ccc-print-phases 2>&1 | FileCheck %s
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3+
// CHECK: [[P0:[0-9]+]]: input, "{{.*}}.c", hip, (device-hip, amdgcnspirv)
4+
// CHECK: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, hip-cpp-output, (device-hip, amdgcnspirv)
5+
// CHECK: [[P2:[0-9]+]]: compiler, {[[P1]]}, ir, (device-hip, amdgcnspirv)
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// CHECK: [[P3:[0-9]+]]: backend, {[[P2]]}, spv, (device-hip, amdgcnspirv)
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// CHECK: [[P4:[0-9]+]]: offload, "device-hip (spirv64-amd-amdhsa:amdgcnspirv)" {[[P3]]}, spv
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// CHECK: [[P5:[0-9]+]]: linker, {[[P4]]}, hip-fatbin, (device-hip, )
9+
// CHECK: [[P6:[0-9]+]]: offload, "device-hip (spirv64-amd-amdhsa:)" {[[P5]]}, hip-fatbin

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