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davemgreendavemgreen
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[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF).
This helps clean up some more legalization artefacts.
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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1074,6 +1074,17 @@ class LegalizationArtifactCombiner {
10741074

10751075
Builder.setInstrAndDebugLoc(MI);
10761076

1077+
if (SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1078+
auto Undef = Builder.buildUndef(DestTy);
1079+
for (unsigned I = 0; I != NumDefs; ++I) {
1080+
Register Def = MI.getReg(I);
1081+
replaceRegOrBuildCopy(Def, Undef.getReg(0), MRI, Builder, UpdatedDefs,
1082+
Observer);
1083+
}
1084+
markInstAndDefDead(MI, *SrcDef, DeadInsts, SrcDefIdx);
1085+
return true;
1086+
}
1087+
10771088
ArtifactValueFinder Finder(MRI, Builder, LI);
10781089
if (Finder.tryCombineUnmergeDefs(MI, Observer, UpdatedDefs)) {
10791090
markInstAndDefDead(MI, *SrcDef, DeadInsts, SrcDefIdx);

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -159,13 +159,16 @@ body: |
159159
; CHECK-LABEL: name: test_freeze_v3s8
160160
; CHECK: liveins: $q0
161161
; CHECK-NEXT: {{ $}}
162-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s8>) = G_IMPLICIT_DEF
163-
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s8>) = G_FREEZE [[DEF]]
164-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[FREEZE]](<4 x s8>)
162+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
163+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
164+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[BUILD_VECTOR]](<8 x s16>)
165+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[TRUNC]](<8 x s8>)
166+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s8>) = G_FREEZE [[UV]]
167+
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[FREEZE]](<4 x s8>)
165168
; CHECK-NEXT: %undef:_(s32) = G_IMPLICIT_DEF
166-
; CHECK-NEXT: %ext0:_(s32) = G_ZEXT [[UV]](s8)
167-
; CHECK-NEXT: %ext1:_(s32) = G_ZEXT [[UV1]](s8)
168-
; CHECK-NEXT: %ext2:_(s32) = G_ZEXT [[UV2]](s8)
169+
; CHECK-NEXT: %ext0:_(s32) = G_ZEXT [[UV2]](s8)
170+
; CHECK-NEXT: %ext1:_(s32) = G_ZEXT [[UV3]](s8)
171+
; CHECK-NEXT: %ext2:_(s32) = G_ZEXT [[UV4]](s8)
169172
; CHECK-NEXT: %res:_(<4 x s32>) = G_BUILD_VECTOR %ext0(s32), %ext1(s32), %ext2(s32), %undef(s32)
170173
; CHECK-NEXT: $q0 = COPY %res(<4 x s32>)
171174
%x:_(<3 x s8>) = G_IMPLICIT_DEF

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -248,21 +248,19 @@ body: |
248248
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s16)
249249
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s16)
250250
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[UV4]](s16)
251-
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(<4 x s8>) = G_IMPLICIT_DEF
252-
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF2]](<4 x s8>)
253-
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[UV6]](s8), [[UV7]](s8), [[UV8]](s8), [[UV6]](s8), [[UV7]](s8), [[UV8]](s8), [[UV6]](s8), [[UV7]](s8), [[UV8]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
254-
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[DEF]](s8), [[DEF]](s8), [[UV6]](s8), [[UV7]](s8), [[UV8]](s8), [[UV6]](s8), [[UV7]](s8), [[UV8]](s8), [[UV6]](s8), [[UV7]](s8), [[UV8]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
251+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
252+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
255253
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR1]](<16 x s8>), [[BUILD_VECTOR2]], shufflemask(0, 16, 16, 16, 1, 16, 16, 16, 2, 16, 16, 16, undef, undef, undef, undef)
256254
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[SHUF]](<16 x s8>)
257255
; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[BITCAST]](<4 x s32>)
258-
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UITOFP]](<4 x s32>)
259-
; CHECK-NEXT: G_STORE [[UV10]](s32), [[COPY]](p0) :: (store (s32), align 16)
256+
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UITOFP]](<4 x s32>)
257+
; CHECK-NEXT: G_STORE [[UV6]](s32), [[COPY]](p0) :: (store (s32), align 16)
260258
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
261259
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
262-
; CHECK-NEXT: G_STORE [[UV11]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4)
260+
; CHECK-NEXT: G_STORE [[UV7]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4)
263261
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
264262
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
265-
; CHECK-NEXT: G_STORE [[UV12]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
263+
; CHECK-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
266264
; CHECK-NEXT: G_BR %bb.1
267265
bb.1:
268266
liveins: $w1, $w2, $w3, $x0

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -220,10 +220,8 @@ body: |
220220
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
221221
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDE]](s32)
222222
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
223-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
224-
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
225223
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[DEF]](s8)
226-
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV8]](s8)
224+
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
227225
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
228226
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV2]], 24
229227
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 23

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -300,24 +300,24 @@ body: |
300300
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s16)
301301
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
302302
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
303-
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
304-
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[UV4]](s16)
305-
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[UV5]](s16)
306-
; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[UV6]](s16)
307-
; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[UV7]](s16)
303+
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
304+
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
305+
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
306+
; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
307+
; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
308308
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8), [[TRUNC8]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
309309
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x s8>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<8 x s8>), [[BUILD_VECTOR1]], shufflemask(0, 0, 0, 0, undef, undef, undef, undef)
310310
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
311311
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[SHUF]](<8 x s8>)
312-
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<4 x s16>), [[UV9:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x s16>)
312+
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x s16>)
313313
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
314314
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR2]](<8 x s8>)
315-
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(<4 x s16>), [[UV11:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT1]](<8 x s16>)
316-
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[UV8]], [[UV10]]
315+
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<4 x s16>), [[UV7:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT1]](<8 x s16>)
316+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[UV4]], [[UV6]]
317317
; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
318318
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[SHUF]](<8 x s8>)
319-
; CHECK-NEXT: [[UV12:%[0-9]+]]:_(<4 x s16>), [[UV13:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT2]](<8 x s16>)
320-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[TRUNC9]], [[UV12]]
319+
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<4 x s16>), [[UV9:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT2]](<8 x s16>)
320+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[TRUNC9]], [[UV8]]
321321
; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
322322
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[TRUNC10]], [[XOR]]
323323
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[AND]], [[AND1]]

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -315,10 +315,9 @@ body: |
315315
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
316316
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
317317
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
318-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
319-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
320-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[UV]](s32)
321-
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[UV]](s32)
318+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
319+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
320+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[DEF]](s32)
322321
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]], shufflemask(0, 1, 5, 6)
323322
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
324323
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SHUF]](<4 x s32>), [[C]](s64)

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -220,10 +220,8 @@ body: |
220220
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
221221
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBE]](s32)
222222
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
223-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
224-
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
225223
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[DEF]](s8)
226-
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV8]](s8)
224+
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
227225
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
228226
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV2]], 24
229227
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 23

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,9 @@ body: |
3737
bb.0:
3838
3939
; CHECK-LABEL: name: test_implicit_def_v4s32
40-
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
41-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
42-
; CHECK-NEXT: $x0 = COPY [[UV]](<2 x s32>)
43-
; CHECK-NEXT: $x1 = COPY [[UV1]](<2 x s32>)
40+
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
41+
; CHECK-NEXT: $x0 = COPY [[DEF]](<2 x s32>)
42+
; CHECK-NEXT: $x1 = COPY [[DEF]](<2 x s32>)
4443
%0:_(<4 x s32>) = G_IMPLICIT_DEF
4544
%1:_(<2 x s32> ), %2:_(<2 x s32>) = G_UNMERGE_VALUES %0
4645
$x0 = COPY %1
@@ -67,10 +66,9 @@ body: |
6766
bb.0:
6867
6968
; CHECK-LABEL: name: test_implicit_def_v2s32
70-
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
71-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
72-
; CHECK-NEXT: $w0 = COPY [[UV]](s32)
73-
; CHECK-NEXT: $w1 = COPY [[UV1]](s32)
69+
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
70+
; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
71+
; CHECK-NEXT: $w1 = COPY [[DEF]](s32)
7472
%0:_(<2 x s32>) = G_IMPLICIT_DEF
7573
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0
7674
$w0 = COPY %1

‎llvm/test/CodeGen/AArch64/dup.ll‎

Lines changed: 47 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2,39 +2,67 @@
22
; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
33
; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

5-
; CHECK-GI: warning: Instruction selection used fallback path for dup_v2i8
6-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for duplane0_v2i8
7-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_v2i8
8-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_str_v2i8
9-
105
define <2 x i8> @dup_v2i8(i8 %a) {
11-
; CHECK-LABEL: dup_v2i8:
12-
; CHECK: // %bb.0: // %entry
13-
; CHECK-NEXT: dup v0.2s, w0
14-
; CHECK-NEXT: ret
6+
; CHECK-SD-LABEL: dup_v2i8:
7+
; CHECK-SD: // %bb.0: // %entry
8+
; CHECK-SD-NEXT: dup v0.2s, w0
9+
; CHECK-SD-NEXT: ret
10+
;
11+
; CHECK-GI-LABEL: dup_v2i8:
12+
; CHECK-GI: // %bb.0: // %entry
13+
; CHECK-GI-NEXT: dup v0.8b, w0
14+
; CHECK-GI-NEXT: umov w8, v0.b[0]
15+
; CHECK-GI-NEXT: umov w9, v0.b[1]
16+
; CHECK-GI-NEXT: fmov s0, w8
17+
; CHECK-GI-NEXT: mov v0.s[1], w9
18+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
19+
; CHECK-GI-NEXT: ret
1520
entry:
1621
%b = insertelement <2 x i8> poison, i8 %a, i64 0
1722
%c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer
1823
ret <2 x i8> %c
1924
}
2025

2126
define <2 x i8> @duplane0_v2i8(<2 x i8> %b) {
22-
; CHECK-LABEL: duplane0_v2i8:
23-
; CHECK: // %bb.0: // %entry
24-
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
25-
; CHECK-NEXT: dup v0.2s, v0.s[0]
26-
; CHECK-NEXT: ret
27+
; CHECK-SD-LABEL: duplane0_v2i8:
28+
; CHECK-SD: // %bb.0: // %entry
29+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
30+
; CHECK-SD-NEXT: dup v0.2s, v0.s[0]
31+
; CHECK-SD-NEXT: ret
32+
;
33+
; CHECK-GI-LABEL: duplane0_v2i8:
34+
; CHECK-GI: // %bb.0: // %entry
35+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
36+
; CHECK-GI-NEXT: mov w8, v0.s[1]
37+
; CHECK-GI-NEXT: mov v0.b[1], w8
38+
; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
39+
; CHECK-GI-NEXT: umov w8, v0.b[0]
40+
; CHECK-GI-NEXT: umov w9, v0.b[1]
41+
; CHECK-GI-NEXT: fmov s0, w8
42+
; CHECK-GI-NEXT: mov v0.s[1], w9
43+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
44+
; CHECK-GI-NEXT: ret
2745
entry:
2846
%c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer
2947
ret <2 x i8> %c
3048
}
3149

3250
define <2 x i8> @loaddup_v2i8(ptr %p) {
33-
; CHECK-LABEL: loaddup_v2i8:
34-
; CHECK: // %bb.0: // %entry
35-
; CHECK-NEXT: ldrb w8, [x0]
36-
; CHECK-NEXT: dup v0.2s, w8
37-
; CHECK-NEXT: ret
51+
; CHECK-SD-LABEL: loaddup_v2i8:
52+
; CHECK-SD: // %bb.0: // %entry
53+
; CHECK-SD-NEXT: ldrb w8, [x0]
54+
; CHECK-SD-NEXT: dup v0.2s, w8
55+
; CHECK-SD-NEXT: ret
56+
;
57+
; CHECK-GI-LABEL: loaddup_v2i8:
58+
; CHECK-GI: // %bb.0: // %entry
59+
; CHECK-GI-NEXT: ld1r { v0.8b }, [x0]
60+
; CHECK-GI-NEXT: umov w8, v0.b[0]
61+
; CHECK-GI-NEXT: umov w9, v0.b[1]
62+
; CHECK-GI-NEXT: fmov s0, w8
63+
; CHECK-GI-NEXT: mov v0.s[1], w9
64+
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
65+
; CHECK-GI-NEXT: ret
3866
entry:
3967
%a = load i8, ptr %p
4068
%b = insertelement <2 x i8> poison, i8 %a, i64 0

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