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[PowerPC] Prefer xxsel for vector selection
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+62
-26
lines changed

5 files changed

+62
-26
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‎llvm/lib/Target/PowerPC/PPCInstrVSX.td‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2707,6 +2707,44 @@ def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
27072707
(XXSEL $vC, $vB, $vA)>;
27082708
def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
27092709
(XXSEL $vC, $vB, $vA)>;
2710+
2711+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETEQ)),
2712+
v4i32:$tval, v4i32:$fval),
2713+
(XXSEL $fval, $tval, (XVCMPEQDP $lhs, $rhs))>;
2714+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETNE)),
2715+
v4i32:$tval, v4i32:$fval),
2716+
(XXSEL $tval, $fval, (XVCMPEQDP $lhs, $rhs))>;
2717+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETGE)),
2718+
v4i32:$tval, v4i32:$fval),
2719+
(XXSEL $fval, $tval, (XVCMPGEDP $lhs, $rhs))>;
2720+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETLT)),
2721+
v4i32:$tval, v4i32:$fval),
2722+
(XXSEL $tval, $fval, (XVCMPGEDP $lhs, $rhs))>;
2723+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETGT)),
2724+
v4i32:$tval, v4i32:$fval),
2725+
(XXSEL $fval, $tval, (XVCMPGTDP $lhs, $rhs))>;
2726+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETLE)),
2727+
v4i32:$tval, v4i32:$fval),
2728+
(XXSEL $tval, $fval, (XVCMPGTDP $lhs, $rhs))>;
2729+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOEQ)),
2730+
v4i32:$tval, v4i32:$fval),
2731+
(XXSEL $fval, $tval, (XVCMPEQDP $lhs, $rhs))>;
2732+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETONE)),
2733+
v4i32:$tval, v4i32:$fval),
2734+
(XXSEL $tval, $fval, (XVCMPEQDP $lhs, $rhs))>;
2735+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOGE)),
2736+
v4i32:$tval, v4i32:$fval),
2737+
(XXSEL $fval, $tval, (XVCMPGEDP $lhs, $rhs))>;
2738+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOLT)),
2739+
v4i32:$tval, v4i32:$fval),
2740+
(XXSEL $tval, $fval, (XVCMPGEDP $lhs, $rhs))>;
2741+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOGT)),
2742+
v4i32:$tval, v4i32:$fval),
2743+
(XXSEL $fval, $tval, (XVCMPGTDP $lhs, $rhs))>;
2744+
def : Pat<(vselect (v4i32 (setcc v4i32:$lhs, v4i32:$rhs, SETOLE)),
2745+
v4i32:$tval, v4i32:$fval),
2746+
(XXSEL $tval, $fval, (XVCMPGTDP $lhs, $rhs))>;
2747+
27102748
def : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)),
27112749
(COPY_TO_REGCLASS
27122750
(XXSEL (COPY_TO_REGCLASS $vC, VSRC),

‎llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1843,10 +1843,10 @@ define <4 x i32> @absd_int32_sgt(<4 x i32>, <4 x i32>) {
18431843
;
18441844
; CHECK-PWR78-LABEL: absd_int32_sgt:
18451845
; CHECK-PWR78: # %bb.0:
1846-
; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
1847-
; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1846+
; CHECK-PWR78-NEXT: xvcmpgtdp vs0, v2, v3
1847+
; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
18481848
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1849-
; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1849+
; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
18501850
; CHECK-PWR78-NEXT: blr
18511851
%3 = icmp sgt <4 x i32> %0, %1
18521852
%4 = sub <4 x i32> %0, %1
@@ -1865,8 +1865,7 @@ define <4 x i32> @absd_int32_sge(<4 x i32>, <4 x i32>) {
18651865
;
18661866
; CHECK-PWR78-LABEL: absd_int32_sge:
18671867
; CHECK-PWR78: # %bb.0:
1868-
; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
1869-
; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1868+
; CHECK-PWR78-NEXT: xvcmpgedp vs0, v2, v3
18701869
; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
18711870
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
18721871
; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
@@ -1888,10 +1887,10 @@ define <4 x i32> @absd_int32_slt(<4 x i32>, <4 x i32>) {
18881887
;
18891888
; CHECK-PWR78-LABEL: absd_int32_slt:
18901889
; CHECK-PWR78: # %bb.0:
1891-
; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
1892-
; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1890+
; CHECK-PWR78-NEXT: xvcmpgedp vs0, v2, v3
1891+
; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
18931892
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1894-
; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1893+
; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
18951894
; CHECK-PWR78-NEXT: blr
18961895
%3 = icmp slt <4 x i32> %0, %1
18971896
%4 = sub <4 x i32> %0, %1
@@ -1910,11 +1909,10 @@ define <4 x i32> @absd_int32_sle(<4 x i32>, <4 x i32>) {
19101909
;
19111910
; CHECK-PWR78-LABEL: absd_int32_sle:
19121911
; CHECK-PWR78: # %bb.0:
1913-
; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
1914-
; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1912+
; CHECK-PWR78-NEXT: xvcmpgtdp vs0, v2, v3
19151913
; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
19161914
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1917-
; CHECK-PWR78-NEXT: xxsel v2, v4, v2, vs0
1915+
; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
19181916
; CHECK-PWR78-NEXT: blr
19191917
%3 = icmp sle <4 x i32> %0, %1
19201918
%4 = sub <4 x i32> %0, %1

‎llvm/test/CodeGen/PowerPC/vec_select.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -86,8 +86,8 @@ entry:
8686
define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
8787
; CHECK-VSX-LABEL: test5:
8888
; CHECK-VSX: # %bb.0: # %entry
89-
; CHECK-VSX-NEXT: vcmpequw v4, v4, v5
90-
; CHECK-VSX-NEXT: xxsel v2, v3, v2, v4
89+
; CHECK-VSX-NEXT: xvcmpeqdp vs0, v4, v5
90+
; CHECK-VSX-NEXT: xxsel v2, v3, v2, vs0
9191
; CHECK-VSX-NEXT: blr
9292
;
9393
; CHECK-NOVSX-LABEL: test5:

‎llvm/test/CodeGen/PowerPC/vselect-constants.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -34,14 +34,14 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
3434
; CHECK: # %bb.0:
3535
; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha
3636
; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha
37-
; CHECK-NEXT: vcmpequw 2, 2, 3
37+
; CHECK-NEXT: xvcmpeqdp 1, 34, 35
3838
; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
3939
; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l
4040
; CHECK-NEXT: lxvd2x 0, 0, 3
41-
; CHECK-NEXT: lxvd2x 1, 0, 4
42-
; CHECK-NEXT: xxswapd 35, 0
43-
; CHECK-NEXT: xxswapd 36, 1
44-
; CHECK-NEXT: xxsel 34, 36, 35, 34
41+
; CHECK-NEXT: lxvd2x 2, 0, 4
42+
; CHECK-NEXT: xxswapd 34, 0
43+
; CHECK-NEXT: xxswapd 35, 2
44+
; CHECK-NEXT: xxsel 34, 35, 34, 1
4545
; CHECK-NEXT: blr
4646
%cond = icmp eq <4 x i32> %x, %y
4747
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>

‎llvm/test/CodeGen/PowerPC/vsx.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -558,26 +558,26 @@ entry:
558558
define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
559559
; CHECK-LABEL: test20:
560560
; CHECK: # %bb.0: # %entry
561-
; CHECK-NEXT: vcmpequw v4, v4, v5
562-
; CHECK-NEXT: xxsel v2, v3, v2, v4
561+
; CHECK-NEXT: xvcmpeqdp vs0, v4, v5
562+
; CHECK-NEXT: xxsel v2, v3, v2, vs0
563563
; CHECK-NEXT: blr
564564
;
565565
; CHECK-REG-LABEL: test20:
566566
; CHECK-REG: # %bb.0: # %entry
567-
; CHECK-REG-NEXT: vcmpequw v4, v4, v5
568-
; CHECK-REG-NEXT: xxsel v2, v3, v2, v4
567+
; CHECK-REG-NEXT: xvcmpeqdp vs0, v4, v5
568+
; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0
569569
; CHECK-REG-NEXT: blr
570570
;
571571
; CHECK-FISL-LABEL: test20:
572572
; CHECK-FISL: # %bb.0: # %entry
573-
; CHECK-FISL-NEXT: vcmpequw v4, v4, v5
574-
; CHECK-FISL-NEXT: xxsel v2, v3, v2, v4
573+
; CHECK-FISL-NEXT: xvcmpeqdp vs0, v4, v5
574+
; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0
575575
; CHECK-FISL-NEXT: blr
576576
;
577577
; CHECK-LE-LABEL: test20:
578578
; CHECK-LE: # %bb.0: # %entry
579-
; CHECK-LE-NEXT: vcmpequw v4, v4, v5
580-
; CHECK-LE-NEXT: xxsel v2, v3, v2, v4
579+
; CHECK-LE-NEXT: xvcmpeqdp vs0, v4, v5
580+
; CHECK-LE-NEXT: xxsel v2, v3, v2, vs0
581581
; CHECK-LE-NEXT: blr
582582
entry:
583583
%m = icmp eq <4 x i32> %c, %d

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