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Reduce testcase, remove -global-isel, drop Attrs comments and check output.
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‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll‎

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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O1 -global-isel=true < %s
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; Function Attrs: nounwind
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define amdgpu_kernel void @test_iglp_opt() #0 {
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entry:
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call void @llvm.amdgcn.iglp.opt(i32 0) #4
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ret void
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}
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; Function Attrs: nounwind
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define amdgpu_kernel void @test_iglp_opt_mfma_gemm(ptr addrspace(3) noalias %in, ptr addrspace(3) noalias %out) #0 {
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entry:
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call void @llvm.amdgcn.iglp.opt(i32 0)
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%idx = call i32 @llvm.amdgcn.workitem.id.x()
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%load.0.addr = getelementptr <32 x float>, ptr addrspace(3) %in, i32 %idx
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%load.0 = load <32 x float>, ptr addrspace(3) %load.0.addr, align 128
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%load.1.addr = getelementptr <32 x float>, ptr addrspace(3) %load.0.addr, i32 64
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%load.1 = load <32 x float>, ptr addrspace(3) %load.1.addr, align 128
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%load.2.addr = getelementptr <32 x float>, ptr addrspace(3) %load.1.addr, i32 128
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%load.2 = load <32 x float>, ptr addrspace(3) %load.2.addr, align 128
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%load.3.addr = getelementptr <32 x float>, ptr addrspace(3) %load.2.addr, i32 192
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%load.3 = load <32 x float>, ptr addrspace(3) %load.3.addr, align 128
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%load.4.addr = getelementptr <32 x float>, ptr addrspace(3) %load.3.addr, i32 256
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%load.4 = load <32 x float>, ptr addrspace(3) %load.4.addr, align 128
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%mai.0 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.0, i32 0, i32 0, i32 0)
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%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.1, i32 0, i32 0, i32 0)
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%mai.2 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.2, i32 0, i32 0, i32 0)
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%mai.3 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.3, i32 0, i32 0, i32 0)
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%mai.4 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.4, i32 0, i32 0, i32 0)
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%store.0.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 %idx
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store <32 x float> %mai.0, ptr addrspace(3) %store.0.addr, align 128
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%store.1.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 64
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store <32 x float> %mai.1, ptr addrspace(3) %store.1.addr, align 128
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%store.2.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 128
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store <32 x float> %mai.2, ptr addrspace(3) %store.2.addr, align 128
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%store.3.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 192
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store <32 x float> %mai.3, ptr addrspace(3) %store.3.addr, align 128
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%store.4.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 256
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store <32 x float> %mai.4, ptr addrspace(3) %store.4.addr, align 128
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ret void
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}
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; Function Attrs: nounwind
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define amdgpu_kernel void @test_iglp_opt_rev_mfma_gemm(ptr addrspace(3) noalias %in, ptr addrspace(3) noalias %out) #0 {
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entry:
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call void @llvm.amdgcn.iglp.opt(i32 1)
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%idx = call i32 @llvm.amdgcn.workitem.id.x()
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%load.0.addr = getelementptr <32 x float>, ptr addrspace(3) %in, i32 %idx
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%load.0 = load <32 x float>, ptr addrspace(3) %load.0.addr, align 128
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%load.1.addr = getelementptr <32 x float>, ptr addrspace(3) %load.0.addr, i32 64
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%load.1 = load <32 x float>, ptr addrspace(3) %load.1.addr, align 128
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%load.2.addr = getelementptr <32 x float>, ptr addrspace(3) %load.1.addr, i32 128
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%load.2 = load <32 x float>, ptr addrspace(3) %load.2.addr, align 128
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%load.3.addr = getelementptr <32 x float>, ptr addrspace(3) %load.2.addr, i32 192
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%L = load <1 x i64>, ptr addrspace(3) %load.3.addr, align 8
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%load.3 = load <32 x float>, ptr addrspace(3) %load.3.addr, align 128
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%load.4.addr = getelementptr <32 x float>, ptr addrspace(3) %load.3.addr, i32 256
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%L1 = load <1 x i64>, ptr addrspace(3) %load.4.addr, align 8
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%load.4 = load <32 x float>, ptr addrspace(3) %load.4.addr, align 128
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%B = urem <1 x i64> %L, %L1
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%mai.0 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.0, i32 0, i32 0, i32 0)
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%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.1, i32 0, i32 0, i32 0)
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%mai.2 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.2, i32 0, i32 0, i32 0)
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%mai.3 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.3, i32 0, i32 0, i32 0)
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%mai.4 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.4, i32 0, i32 0, i32 0)
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%store.0.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 %idx
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store <32 x float> %mai.0, ptr addrspace(3) %store.0.addr, align 128
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%store.1.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 64
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store <32 x float> %mai.1, ptr addrspace(3) %store.1.addr, align 128
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%store.2.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 128
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store <32 x float> %mai.2, ptr addrspace(3) %store.2.addr, align 128
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%store.3.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 192
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store <32 x float> %mai.3, ptr addrspace(3) %store.3.addr, align 128
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%store.4.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 256
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store <32 x float> %mai.4, ptr addrspace(3) %store.4.addr, align 128
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store <1 x i64> %B, ptr addrspace(3) %store.3.addr, align 8
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ret void
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}
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; Function Attrs: convergent nocallback nofree nounwind willreturn
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declare void @llvm.amdgcn.iglp.opt(i32 immarg) #1
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32 immarg, i32 immarg, i32 immarg) #3
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attributes #0 = { nounwind "amdgpu-flat-work-group-size"="1,256" }
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attributes #1 = { convergent nocallback nofree nounwind willreturn }
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attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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attributes #3 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #4 = { convergent nounwind }
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O1 < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @test_iglp_opt_rev_mfma_gemm(<1 x i64> %L1) {
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; GCN-LABEL: test_iglp_opt_rev_mfma_gemm:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_mov_b32_e32 v32, 0
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GCN-NEXT: ds_read_b128 v[28:31], v32 offset:112
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; GCN-NEXT: ds_read_b128 v[24:27], v32 offset:96
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; GCN-NEXT: ds_read_b128 v[20:23], v32 offset:80
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; GCN-NEXT: ds_read_b128 v[16:19], v32 offset:64
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; GCN-NEXT: ds_read_b128 v[0:3], v32
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; GCN-NEXT: ds_read_b128 v[4:7], v32 offset:16
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; GCN-NEXT: ds_read_b128 v[8:11], v32 offset:32
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; GCN-NEXT: ds_read_b128 v[12:15], v32 offset:48
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; GCN-NEXT: v_mov_b32_e32 v34, 0
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; GCN-NEXT: v_mov_b32_e32 v35, v34
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
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; GCN-NEXT: ; iglp_opt mask(0x00000001)
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; GCN-NEXT: ds_write_b128 v32, v[28:31] offset:112
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; GCN-NEXT: ds_write_b128 v32, v[24:27] offset:96
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; GCN-NEXT: ds_write_b128 v32, v[20:23] offset:80
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; GCN-NEXT: ds_write_b128 v32, v[16:19] offset:64
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; GCN-NEXT: ds_write_b128 v32, v[12:15] offset:48
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; GCN-NEXT: ds_write_b128 v32, v[8:11] offset:32
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; GCN-NEXT: ds_write_b128 v32, v[4:7] offset:16
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; GCN-NEXT: ds_write_b128 v32, v[0:3]
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; GCN-NEXT: ds_write_b64 v32, v[34:35]
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; GCN-NEXT: s_endpgm
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entry:
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call void @llvm.amdgcn.iglp.opt(i32 1)
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%load.4 = load <32 x float>, ptr addrspace(3) null, align 128
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%B = urem <1 x i64> zeroinitializer, %L1
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store <32 x float> %load.4, ptr addrspace(3) null, align 128
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store <1 x i64> %B, ptr addrspace(3) null, align 8
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ret void
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}
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declare void @llvm.amdgcn.iglp.opt(i32 immarg) #0
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attributes #0 = { convergent nocallback nofree nounwind willreturn }

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