@@ -197,6 +197,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
197197
198198 bool selectOverflowArith (Register ResVReg, const SPIRVType *ResType,
199199 MachineInstr &I, unsigned Opcode) const ;
200+ bool selectDebugTrap (Register ResVReg, const SPIRVType *ResType,
201+ MachineInstr &I) const ;
200202
201203 bool selectIntegerDot (Register ResVReg, const SPIRVType *ResType,
202204 MachineInstr &I, bool Signed) const ;
@@ -951,16 +953,26 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
951953 // represent code after lowering or intrinsics which are not implemented but
952954 // should not crash when found in a customer's LLVM IR input.
953955 case TargetOpcode::G_TRAP:
954- case TargetOpcode::G_DEBUGTRAP:
955956 case TargetOpcode::G_UBSANTRAP:
956957 case TargetOpcode::DBG_LABEL:
957958 return true ;
959+ case TargetOpcode::G_DEBUGTRAP:
960+ return selectDebugTrap (ResVReg, ResType, I);
958961
959962 default :
960963 return false ;
961964 }
962965}
963966
967+ bool SPIRVInstructionSelector::selectDebugTrap (Register ResVReg,
968+ const SPIRVType *ResType,
969+ MachineInstr &I) const {
970+ unsigned Opcode = SPIRV::OpNop;
971+ MachineBasicBlock &BB = *I.getParent ();
972+ return BuildMI (BB, I, I.getDebugLoc (), TII.get (Opcode))
973+ .constrainAllUses (TII, TRI, RBI);
974+ }
975+
964976bool SPIRVInstructionSelector::selectExtInst (Register ResVReg,
965977 const SPIRVType *ResType,
966978 MachineInstr &I,
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