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kperkper
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Added RISCV reg test for the ServerTargetXML
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‎lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py‎

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@@ -652,6 +652,155 @@ def haltReason(self):
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)
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self.match("register read s31", ["s31 = 128"])
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@skipIfXmlSupportMissing
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@skipIfRemote
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@skipIfLLVMTargetMissing("RISCV")
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def test_riscv64_regs(self):
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"""Test grabbing various riscv64 registers from gdbserver."""
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class MyResponder(MockGDBServerResponder):
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reg_data = (
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(
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"0102030405060708" # zero
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"0102030405060708" # ra
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"0102030405060708" # sp
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"0102030405060708" # gp
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"0102030405060708" # tp
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"0102030405060708" # t0
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"0102030405060708" # t1
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"0102030405060708" # t2
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"0102030405060708" # fp
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"0102030405060708" # s1
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"0102030405060708" # a0
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"0102030405060708" # a1
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"0102030405060708" # a2
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"0102030405060708" # a3
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"0102030405060708" # a4
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"0102030405060708" # a5
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"0102030405060708" # a6
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"0102030405060708" # a7
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"0102030405060708" # s2
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"0102030405060708" # s3
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"0102030405060708" # s4
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"0102030405060708" # s5
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"0102030405060708" # s6
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"0102030405060708" # s7
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"0102030405060708" # s8
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"0102030405060708" # s9
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"0102030405060708" # s10
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"0102030405060708" # s11
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"0102030405060708" # t3
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"0102030405060708" # t4
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"0102030405060708" # t5
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"0102030405060708" # t6
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)
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)
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return (
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"""<?xml version="1.0"?>
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<target>
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<architecture>riscv</architecture>
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<feature name="org.gnu.gdb.riscv.cpu">
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<reg name="zero" bitsize="64" type="int"/>
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<reg name="ra" bitsize="64" type="code_ptr"/>
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<reg name="sp" bitsize="64" type="data_ptr"/>
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<reg name="gp" bitsize="64" type="data_ptr"/>
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<reg name="tp" bitsize="64" type="data_ptr"/>
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<reg name="t0" bitsize="64" type="int"/>
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<reg name="t1" bitsize="64" type="int"/>
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<reg name="t2" bitsize="64" type="int"/>
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<reg name="fp" bitsize="64" type="data_ptr"/>
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<reg name="s1" bitsize="64" type="int"/>
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<reg name="a0" bitsize="64" type="int"/>
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<reg name="a1" bitsize="64" type="int"/>
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<reg name="a2" bitsize="64" type="int"/>
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<reg name="a3" bitsize="64" type="int"/>
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<reg name="a4" bitsize="64" type="int"/>
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<reg name="a5" bitsize="64" type="int"/>
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<reg name="a6" bitsize="64" type="int"/>
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<reg name="a7" bitsize="64" type="int"/>
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<reg name="s2" bitsize="64" type="int"/>
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<reg name="s3" bitsize="64" type="int"/>
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<reg name="s4" bitsize="64" type="int"/>
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<reg name="s5" bitsize="64" type="int"/>
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<reg name="s6" bitsize="64" type="int"/>
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<reg name="s7" bitsize="64" type="int"/>
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<reg name="s8" bitsize="64" type="int"/>
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<reg name="s9" bitsize="64" type="int"/>
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<reg name="s10" bitsize="64" type="int"/>
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<reg name="s11" bitsize="64" type="int"/>
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<reg name="t3" bitsize="64" type="int"/>
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<reg name="t4" bitsize="64" type="int"/>
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<reg name="t5" bitsize="64" type="int"/>
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<reg name="t6" bitsize="64" type="int"/>
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<reg name="pc" bitsize="64" type="code_ptr"/>
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</feature>
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</target>""",
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False,
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)
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else:
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return None, False
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def readRegister(self, regnum):
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return ""
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def readRegisters(self):
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return self.reg_data
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def writeRegisters(self, reg_hex):
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self.reg_data = reg_hex
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return "OK"
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def haltReason(self):
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return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"
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self.server.responder = MyResponder()
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target = self.createTarget("basic_eh_frame-riscv64.yaml")
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process = self.connect(target)
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lldbutil.expect_state_changes(
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self, self.dbg.GetListener(), process, [lldb.eStateStopped]
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)
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# test generic aliases
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self.match("register read x0", ["zero = 0x0807060504030201"])
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self.match("register read x1", ["ra = 0x0807060504030201"])
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self.match("register read x2", ["sp = 0x0807060504030201"])
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self.match("register read x3", ["gp = 0x0807060504030201"])
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self.match("register read x4", ["tp = 0x0807060504030201"])
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self.match("register read x5", ["t0 = 0x0807060504030201"])
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self.match("register read x6", ["t1 = 0x0807060504030201"])
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self.match("register read x7", ["t2 = 0x0807060504030201"])
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# Register x8 is probably not working because it has two aliases fp, s0
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# self.match("register read x8", ["fp = 0x0807060504030201"])
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self.match("register read x9", ["s1 = 0x0807060504030201"])
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self.match("register read x10", ["a0 = 0x0807060504030201"])
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self.match("register read x11", ["a1 = 0x0807060504030201"])
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self.match("register read x12", ["a2 = 0x0807060504030201"])
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self.match("register read x13", ["a3 = 0x0807060504030201"])
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self.match("register read x14", ["a4 = 0x0807060504030201"])
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self.match("register read x15", ["a5 = 0x0807060504030201"])
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self.match("register read x16", ["a6 = 0x0807060504030201"])
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self.match("register read x17", ["a7 = 0x0807060504030201"])
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self.match("register read x18", ["s2 = 0x0807060504030201"])
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self.match("register read x19", ["s3 = 0x0807060504030201"])
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self.match("register read x20", ["s4 = 0x0807060504030201"])
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self.match("register read x21", ["s5 = 0x0807060504030201"])
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self.match("register read x22", ["s6 = 0x0807060504030201"])
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self.match("register read x23", ["s7 = 0x0807060504030201"])
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self.match("register read x24", ["s8 = 0x0807060504030201"])
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self.match("register read x25", ["s9 = 0x0807060504030201"])
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self.match("register read x26", ["s10 = 0x0807060504030201"])
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self.match("register read x27", ["s11 = 0x0807060504030201"])
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self.match("register read x28", ["t3 = 0x0807060504030201"])
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self.match("register read x29", ["t4 = 0x0807060504030201"])
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self.match("register read x30", ["t5 = 0x0807060504030201"])
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self.match("register read x31", ["t6 = 0x0807060504030201"])
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@skipIfXmlSupportMissing
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@skipIfRemote
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@skipIfLLVMTargetMissing("X86")

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