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--Changes in Name of extensions from INTEL to ALTERA.
1 parent d33c51b commit 09b60b8

19 files changed

+121
-122
lines changed

‎llvm/docs/SPIRVUsage.rst‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ Static Compiler Commands
3030
Description: This command compiles an LLVM IL file (`input.ll`) to a SPIR-V binary (`output.spvt`) for a 32-bit architecture.
3131

3232
2. **Compilation with Extensions and Optimization**
33-
Command: `llc -O1 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_integers input.ll -o output.spvt`
34-
Description: Compiles an LLVM IL file to SPIR-V with (`-O1`) optimizations, targeting a 64-bit architecture. It enables the SPV_INTEL_arbitrary_precision_integers extension.
33+
Command: `llc -O1 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers input.ll -o output.spvt`
34+
Description: Compiles an LLVM IL file to SPIR-V with (`-O1`) optimizations, targeting a 64-bit architecture. It enables the SPV_ALTERA_arbitrary_precision_integers extension.
3535

3636
3. **Compilation with experimental NonSemantic.Shader.DebugInfo.100 support**
3737
Command: `llc --spv-emit-nonsemantic-debug-info --spirv-ext=+SPV_KHR_non_semantic_info input.ll -o output.spvt`
@@ -136,7 +136,7 @@ extensions to enable or disable, each prefixed with ``+`` or ``-``, respectively
136136

137137
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
138138

139-
``-spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_INTEL_arbitrary_precision_integers``
139+
``-spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_ALTERA_arbitrary_precision_integers``
140140

141141
To enable all extensions, use the following option:
142142
``-spirv-ext=all``
@@ -145,7 +145,7 @@ To enable all KHR extensions, use the following option:
145145
``-spirv-ext=khr``
146146

147147
To enable all extensions except specified, specify ``all`` followed by a list of disallowed extensions. For example:
148-
``-spirv-ext=all,-SPV_INTEL_arbitrary_precision_integers``
148+
``-spirv-ext=all,-SPV_ALTERA_arbitrary_precision_integers``
149149

150150
Below is a list of supported SPIR-V extensions, sorted alphabetically by their extension names:
151151

@@ -169,7 +169,7 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
169169
- Adds atomic min and max instruction on floating-point numbers.
170170
* - ``SPV_INTEL_2d_block_io``
171171
- Adds additional subgroup block prefetch, load, load transposed, load transformed and store instructions to read two-dimensional blocks of data from a two-dimensional region of memory, or to write two-dimensional blocks of data to a two dimensional region of memory.
172-
* - ``SPV_INTEL_arbitrary_precision_integers``
172+
* - ``SPV_ALTERA_arbitrary_precision_integers``
173173
- Allows generating arbitrary width integer types.
174174
* - ``SPV_INTEL_bindless_images``
175175
- Adds instructions to convert convert unsigned integer handles to images, samplers and sampled images.
@@ -241,8 +241,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
241241
- Adds predicated load and store instructions that conditionally read from or write to memory based on a boolean predicate.
242242
* - ``SPV_KHR_maximal_reconvergence``
243243
- Adds execution mode and capability to enable maximal reconvergence.
244-
* - ``SPV_INTEL_arbitrary_precision_fixed_point``
245-
- Add instructions for fixed point arithmetic. The extension works without SPV_INTEL_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
244+
* - ``SPV_ALTERA_arbitrary_precision_fixed_point``
245+
- Add instructions for fixed point arithmetic. The extension works without SPV_ALTERA_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
246246

247247

248248
SPIR-V representation in LLVM IR

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1177,18 +1177,18 @@ defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelCl
11771177
defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11781178
defm : DemangledNativeBuiltin<"__spirv_ReadClockKHR", OpenCL_std, KernelClock, 1, 1, OpReadClockKHR>;
11791179

1180-
//SPV_INTEL_arbitrary_precision_fixed_point
1181-
defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
1182-
defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
1183-
defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
1184-
defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
1185-
defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
1186-
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
1187-
defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
1188-
defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
1189-
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
1190-
defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
1191-
defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
1180+
//SPV_ALTERA_arbitrary_precision_fixed_point
1181+
defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtALTERA>;
1182+
defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipALTERA>;
1183+
defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtALTERA>;
1184+
defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinALTERA>;
1185+
defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosALTERA>;
1186+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosALTERA>;
1187+
defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiALTERA>;
1188+
defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiALTERA>;
1189+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiALTERA>;
1190+
defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogALTERA>;
1191+
defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpALTERA>;
11921192

11931193
//===----------------------------------------------------------------------===//
11941194
// Class defining an atomic instruction on floating-point numbers.

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,8 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
5151
SPIRV::Extension::Extension::SPV_GOOGLE_hlsl_functionality1},
5252
{"SPV_GOOGLE_user_type",
5353
SPIRV::Extension::Extension::SPV_GOOGLE_user_type},
54-
{"SPV_INTEL_arbitrary_precision_integers",
55-
SPIRV::Extension::Extension::SPV_INTEL_arbitrary_precision_integers},
54+
{"SPV_ALTERA_arbitrary_precision_integers",
55+
SPIRV::Extension::Extension::SPV_ALTERA_arbitrary_precision_integers},
5656
{"SPV_INTEL_cache_controls",
5757
SPIRV::Extension::Extension::SPV_INTEL_cache_controls},
5858
{"SPV_INTEL_float_controls2",
@@ -161,9 +161,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
161161
{"SPV_INTEL_kernel_attributes",
162162
SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes},
163163
{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
164-
{"SPV_INTEL_arbitrary_precision_fixed_point",
164+
{"SPV_ALTERA_arbitrary_precision_fixed_point",
165165
SPIRV::Extension::Extension::
166-
SPV_INTEL_arbitrary_precision_fixed_point}};
166+
SPV_ALTERA_arbitrary_precision_fixed_point}};
167167

168168
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
169169
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,7 @@ unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
153153
report_fatal_error("Unsupported integer width!");
154154
const SPIRVSubtarget &ST = cast<SPIRVSubtarget>(CurMF->getSubtarget());
155155
if (ST.canUseExtension(
156-
SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
156+
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
157157
ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4))
158158
return Width;
159159
if (Width <= 8)
@@ -181,11 +181,11 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,
181181
.addImm(SPIRV::Capability::Int4TypeINTEL);
182182
} else if ((!isPowerOf2_32(Width) || Width < 8) &&
183183
ST.canUseExtension(
184-
SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers)) {
184+
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers)) {
185185
MIRBuilder.buildInstr(SPIRV::OpExtension)
186-
.addImm(SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers);
186+
.addImm(SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers);
187187
MIRBuilder.buildInstr(SPIRV::OpCapability)
188-
.addImm(SPIRV::Capability::ArbitraryPrecisionIntegersINTEL);
188+
.addImm(SPIRV::Capability::ArbitraryPrecisionIntegersALTERA);
189189
}
190190
return MIRBuilder.buildInstr(SPIRV::OpTypeInt)
191191
.addDef(createTypeVReg(MIRBuilder))

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -994,26 +994,26 @@ def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr,
994994
def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
995995
"OpPredicatedStoreINTEL $ptr $object $predicate">;
996996

997-
//SPV_INTEL_arbitrary_precision_fixed_point
998-
def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
999-
"$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
1000-
def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1001-
"$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
1002-
def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1003-
"$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
1004-
def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1005-
"$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
1006-
def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1007-
"$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
1008-
def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1009-
"$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
1010-
def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1011-
"$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
1012-
def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1013-
"$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
1014-
def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1015-
"$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
1016-
def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1017-
"$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
1018-
def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1019-
"$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
997+
//SPV_ALTERA_arbitrary_precision_fixed_point
998+
def OpFixedSqrtALTERA: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
999+
"$res = OpFixedSqrtALTERA $result_type $input $sign $l $rl $q $o">;
1000+
def OpFixedRecipALTERA: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1001+
"$res = OpFixedRecipALTERA $result_type $input $sign $l $rl $q $o">;
1002+
def OpFixedRsqrtALTERA: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1003+
"$res = OpFixedRsqrtALTERA $result_type $input $sign $l $rl $q $o">;
1004+
def OpFixedSinALTERA: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1005+
"$res = OpFixedSinALTERA $result_type $input $sign $l $rl $q $o">;
1006+
def OpFixedCosALTERA: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1007+
"$res = OpFixedCosALTERA $result_type $input $sign $l $rl $q $o">;
1008+
def OpFixedSinCosALTERA: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1009+
"$res = OpFixedSinCosALTERA $result_type $input $sign $l $rl $q $o">;
1010+
def OpFixedSinPiALTERA: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1011+
"$res = OpFixedSinPiALTERA $result_type $input $sign $l $rl $q $o">;
1012+
def OpFixedCosPiALTERA: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1013+
"$res = OpFixedCosPiALTERA $result_type $input $sign $l $rl $q $o">;
1014+
def OpFixedSinCosPiALTERA: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1015+
"$res = OpFixedSinCosPiALTERA $result_type $input $sign $l $rl $q $o">;
1016+
def OpFixedLogALTERA: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1017+
"$res = OpFixedLogALTERA $result_type $input $sign $l $rl $q $o">;
1018+
def OpFixedExpALTERA: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1019+
"$res = OpFixedExpALTERA $result_type $input $sign $l $rl $q $o">;

‎llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
128128

129129
bool IsExtendedInts =
130130
ST.canUseExtension(
131-
SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
131+
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
132132
ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions) ||
133133
ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4);
134134
auto extendedScalarsAndVectors =

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1670,26 +1670,26 @@ void addInstrRequirements(const MachineInstr &MI,
16701670
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
16711671
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
16721672
break;
1673-
case SPIRV::OpFixedCosINTEL:
1674-
case SPIRV::OpFixedSinINTEL:
1675-
case SPIRV::OpFixedCosPiINTEL:
1676-
case SPIRV::OpFixedSinPiINTEL:
1677-
case SPIRV::OpFixedExpINTEL:
1678-
case SPIRV::OpFixedLogINTEL:
1679-
case SPIRV::OpFixedRecipINTEL:
1680-
case SPIRV::OpFixedSqrtINTEL:
1681-
case SPIRV::OpFixedSinCosINTEL:
1682-
case SPIRV::OpFixedSinCosPiINTEL:
1683-
case SPIRV::OpFixedRsqrtINTEL:
1673+
case SPIRV::OpFixedCosALTERA:
1674+
case SPIRV::OpFixedSinALTERA:
1675+
case SPIRV::OpFixedCosPiALTERA:
1676+
case SPIRV::OpFixedSinPiALTERA:
1677+
case SPIRV::OpFixedExpALTERA:
1678+
case SPIRV::OpFixedLogALTERA:
1679+
case SPIRV::OpFixedRecipALTERA:
1680+
case SPIRV::OpFixedSqrtALTERA:
1681+
case SPIRV::OpFixedSinCosALTERA:
1682+
case SPIRV::OpFixedSinCosPiALTERA:
1683+
case SPIRV::OpFixedRsqrtALTERA:
16841684
if (!ST.canUseExtension(
1685-
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
1685+
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_fixed_point))
16861686
report_fatal_error("This instruction requires the "
16871687
"following SPIR-V extension: "
1688-
"SPV_INTEL_arbitrary_precision_fixed_point",
1688+
"SPV_ALTERA_arbitrary_precision_fixed_point",
16891689
false);
16901690
Reqs.addExtension(
1691-
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
1692-
Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
1691+
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_fixed_point);
1692+
Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointALTERA);
16931693
break;
16941694
case SPIRV::OpGroupIMulKHR:
16951695
case SPIRV::OpGroupFMulKHR:

‎llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -509,7 +509,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
509509

510510
bool IsExtendedInts =
511511
ST->canUseExtension(
512-
SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers) ||
512+
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
513513
ST->canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions) ||
514514
ST->canUseExtension(SPIRV::Extension::SPV_INTEL_int4);
515515

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