Skip to content

Commit 09d745a

Browse files
committed
Remove driveby formatting fixes
1 parent 7a6fe79 commit 09d745a

File tree

3 files changed

+6
-9
lines changed

3 files changed

+6
-9
lines changed

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4314,7 +4314,6 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
43144314
return DAG.getNode(ISD::BITCAST, SL, VT, Vec);
43154315
}
43164316

4317-
43184317
SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
43194318
DAGCombinerInfo &DCI) const {
43204319
SDValue RHS = N->getOperand(1);
@@ -4841,8 +4840,8 @@ AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
48414840
if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))
48424841
return SDValue();
48434842

4844-
return distributeOpThroughSelect(DCI, LHS.getOpcode(), SDLoc(N), Cond, LHS,
4845-
RHS);
4843+
return distributeOpThroughSelect(DCI, LHS.getOpcode(),
4844+
SDLoc(N), Cond, LHS, RHS);
48464845
}
48474846

48484847
bool Inv = false;

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13388,8 +13388,6 @@ SDValue SITargetLowering::performXorCombine(SDNode *N,
1338813388
return XSelect;
1338913389
}
1339013390

13391-
13392-
1339313391
// Make sure to apply the 64-bit constant splitting fold before trying to fold
1339413392
// fneg-like xors into 64-bit select.
1339513393
if (LHS.getOpcode() == ISD::SELECT && VT == MVT::i32) {
@@ -14435,10 +14433,9 @@ SITargetLowering::performExtractVectorEltCombine(SDNode *N,
1443514433
if (!DCI.isBeforeLegalize())
1443614434
return SDValue();
1443714435

14438-
// Try to turn sub-dword accesses of vectors into accesses of the same
14439-
// 32-bit elements. This exposes more load reduction opportunities by
14440-
// replacing multiple small extract_vector_elements with a single 32-bit
14441-
// extract.
14436+
// Try to turn sub-dword accesses of vectors into accesses of the same 32-bit
14437+
// elements. This exposes more load reduction opportunities by replacing
14438+
// multiple small extract_vector_elements with a single 32-bit extract.
1444214439
auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
1444314440
if (isa<MemSDNode>(Vec) && VecEltSize <= 16 && VecEltVT.isByteSized() &&
1444414441
VecSize > 32 && VecSize % 32 == 0 && Idx) {

llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1903,6 +1903,7 @@ def : GCNPat <
19031903
>;
19041904
}
19051905

1906+
19061907
/********** ================================ **********/
19071908
/********** Floating point absolute/negative **********/
19081909
/********** ================================ **********/

0 commit comments

Comments
 (0)