@@ -83,8 +83,8 @@ void VirtRegMap::grow() {
8383 Virt2SplitMap.resize (NumRegs);
8484}
8585
86- void VirtRegMap::assignVirt2Phys (Register virtReg, MCPhysReg physReg) {
87- assert (virtReg.isVirtual () && Register::isPhysicalRegister ( physReg));
86+ void VirtRegMap::assignVirt2Phys (Register virtReg, MCRegister physReg) {
87+ assert (virtReg.isVirtual () && physReg. isPhysical ( ));
8888 assert (!Virt2PhysMap[virtReg] &&
8989 " attempt to assign physical register to already mapped "
9090 " virtual register" );
@@ -221,7 +221,7 @@ class VirtRegRewriter : public MachineFunctionPass {
221221 bool subRegLiveThrough (const MachineInstr &MI, MCRegister SuperPhysReg) const ;
222222 LaneBitmask liveOutUndefPhiLanesForUndefSubregDef (
223223 const LiveInterval &LI, const MachineBasicBlock &MBB, unsigned SubReg,
224- MCPhysReg PhysReg, const MachineInstr &MI) const ;
224+ MCRegister PhysReg, const MachineInstr &MI) const ;
225225
226226public:
227227 static char ID;
@@ -563,7 +563,7 @@ bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
563563// / is assigned to \p LI, which is the main range.
564564LaneBitmask VirtRegRewriter::liveOutUndefPhiLanesForUndefSubregDef (
565565 const LiveInterval &LI, const MachineBasicBlock &MBB, unsigned SubReg,
566- MCPhysReg PhysReg, const MachineInstr &MI) const {
566+ MCRegister PhysReg, const MachineInstr &MI) const {
567567 LaneBitmask UndefMask = ~TRI->getSubRegIndexLaneMask (SubReg);
568568 LaneBitmask LiveOutUndefLanes;
569569
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