Prefer readable condition

justinfargnoli · justinfargnoli · commit 0aadf98c856e · 2024-09-15T15:25:06.000-07:00
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34447,7 +34447,7 @@ bool X86TargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
 
 bool X86TargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
   // i16 instructions are longer (0x66 prefix) and potentially slower.
-  if (SrcVT.isVector() || DestVT.isVector())
+  if (!(SrcVT.isScalarInteger() && DestVT.isScalarInteger()))
     return false;
   return !(SrcVT == MVT::i32 && DestVT == MVT::i16);
 }

Original file line number	Diff line number	Diff line change
`@@ -34447,7 +34447,7 @@ bool X86TargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,`
`34447`	`34447`
`34448`	`34448`	`bool X86TargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {`
`34449`	`34449`	`// i16 instructions are longer (0x66 prefix) and potentially slower.`
`34450`		`- if (SrcVT.isVector() \|\| DestVT.isVector())`
	`34450`	`+ if (!(SrcVT.isScalarInteger() && DestVT.isScalarInteger()))`
`34451`	`34451`	`return false;`
`34452`	`34452`	`return !(SrcVT == MVT::i32 && DestVT == MVT::i16);`
`34453`	`34453`	`}`