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kperkper
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[DAG] Fold rem(rem(A, BCst), Op1Cst) -> rem(A, Op1Cst) (#159517)
Fixes [157370](#157370) UREM General proof: https://alive2.llvm.org/ce/z/b_GQJX SREM General proof: https://alive2.llvm.org/ce/z/Whkaxh I have added it as rv32i and rv64i tests because they are the only architectures where I could verify that it works.
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -5442,6 +5442,24 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
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if (SDValue DivRem = useDivRem(N))
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return DivRem.getValue(1);
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// fold urem(urem(A, BCst), Op1Cst) -> urem(A, Op1Cst)
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// iff urem(BCst, Op1Cst) == 0
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SDValue A;
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APInt Op1Cst, BCst;
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if (sd_match(N, m_URem(m_URem(m_Value(A), m_ConstInt(BCst)),
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m_ConstInt(Op1Cst))) &&
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BCst.urem(Op1Cst).isZero()) {
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return DAG.getNode(ISD::UREM, DL, VT, A, DAG.getConstant(Op1Cst, DL, VT));
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}
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// fold srem(srem(A, BCst), Op1Cst) -> srem(A, Op1Cst)
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// iff srem(BCst, Op1Cst) == 0 && Op1Cst != 1
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if (sd_match(N, m_SRem(m_SRem(m_Value(A), m_ConstInt(BCst)),
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m_ConstInt(Op1Cst))) &&
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BCst.srem(Op1Cst).isZero() && !Op1Cst.isAllOnes()) {
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return DAG.getNode(ISD::SREM, DL, VT, A, DAG.getConstant(Op1Cst, DL, VT));
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}
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return SDValue();
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}
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‎llvm/test/CodeGen/RISCV/srem.ll‎

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@@ -0,0 +1,57 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
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define i32 @fold_srem_constants(i32 %v0) nounwind {
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; RV32I-LABEL: fold_srem_constants:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a1, 5
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; RV32I-NEXT: tail __modsi3
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;
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; RV64I-LABEL: fold_srem_constants:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: li a1, 5
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%v1 = srem i32 %v0, 25
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%v2 = srem i32 %v1, 5
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ret i32 %v2
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}
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define i32 @dont_fold_srem_constants(i32 %v0) nounwind {
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; RV32I-LABEL: dont_fold_srem_constants:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: li a1, 25
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; RV32I-NEXT: call __modsi3
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; RV32I-NEXT: li a1, 3
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: tail __modsi3
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;
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; RV64I-LABEL: dont_fold_srem_constants:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: li a1, 25
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: li a1, 3
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%v1 = srem i32 %v0, 25
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%v2 = srem i32 %v1, 3
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ret i32 %v2
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}

‎llvm/test/CodeGen/RISCV/urem.ll‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
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define i32 @fold_urem_constants(i32 %v0) nounwind {
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; RV32I-LABEL: fold_urem_constants:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a1, 5
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; RV32I-NEXT: tail __umodsi3
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;
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; RV64I-LABEL: fold_urem_constants:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: li a1, 5
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; RV64I-NEXT: call __umoddi3
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%v1 = urem i32 %v0, 25
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%v2 = urem i32 %v1, 5
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ret i32 %v2
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}
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define i32 @dont_fold_urem_constants(i32 %v0) nounwind {
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; RV32I-LABEL: dont_fold_urem_constants:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: li a1, 25
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; RV32I-NEXT: call __umodsi3
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; RV32I-NEXT: li a1, 3
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: tail __umodsi3
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;
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; RV64I-LABEL: dont_fold_urem_constants:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: li a1, 25
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; RV64I-NEXT: call __umoddi3
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; RV64I-NEXT: li a1, 3
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; RV64I-NEXT: call __umoddi3
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%v1 = urem i32 %v0, 25
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%v2 = urem i32 %v1, 3
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ret i32 %v2
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}
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define i32 @dont_fold_urem_srem_mixed_constants(i32 %v0) nounwind {
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; RV32I-LABEL: dont_fold_urem_srem_mixed_constants:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: li a1, 25
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; RV32I-NEXT: call __umodsi3
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; RV32I-NEXT: li a1, 3
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: tail __umodsi3
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;
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; RV64I-LABEL: dont_fold_urem_srem_mixed_constants:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: li a1, 25
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; RV64I-NEXT: call __umoddi3
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; RV64I-NEXT: li a1, 3
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; RV64I-NEXT: call __umoddi3
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%v1 = urem i32 %v0, 25
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%v2 = srem i32 %v1, 3
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ret i32 %v2
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}
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define i32 @dont_fold_srem_urem_mixed_constants(i32 %v0) nounwind {
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; RV32I-LABEL: dont_fold_srem_urem_mixed_constants:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: li a1, 25
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; RV32I-NEXT: call __modsi3
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; RV32I-NEXT: li a1, 3
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: tail __umodsi3
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;
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; RV64I-LABEL: dont_fold_srem_urem_mixed_constants:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: li a1, 25
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; RV64I-NEXT: call __moddi3
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: li a1, 3
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; RV64I-NEXT: call __umoddi3
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%v1 = srem i32 %v0, 25
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%v2 = urem i32 %v1, 3
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ret i32 %v2
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}

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