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3 files changed

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‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1748,9 +1748,11 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
17481748
(ins Src0Mod:$src0_modifiers, Src0RC:$src0)))
17491749
/* else */,
17501750
// VOP1 without modifiers
1751-
!if (HasClamp,
1752-
(ins Src0RC:$src0, Clamp0:$clamp),
1753-
(ins Src0RC:$src0))
1751+
!if(HasOMod,
1752+
(ins Src0RC:$src0, Clamp0:$clamp, omod0:$omod),
1753+
!if (HasClamp,
1754+
(ins Src0RC:$src0, Clamp0:$clamp),
1755+
(ins Src0RC:$src0)))
17541756
/* endif */ ),
17551757
!if (!eq(NumSrcArgs, 2),
17561758
!if (HasModifiers,
@@ -2538,6 +2540,7 @@ class VOPProfile_Fake16<VOPProfile P> : VOPProfile<P.ArgVT> {
25382540
// Most DstVT are 16-bit, but not all
25392541
let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
25402542
let DstRC64 = getVALUDstForVT<DstVT>.ret;
2543+
let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
25412544
let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
25422545
let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
25432546
let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1173,9 +1173,12 @@ multiclass f16_fp_Pats<Instruction cvt_f16_f32_inst_e64, Instruction cvt_f32_f16
11731173
let SubtargetPredicate = NotHasTrue16BitInsts in
11741174
defm : f16_fp_Pats<V_CVT_F16_F32_e64, V_CVT_F32_F16_e64>;
11751175

1176-
let SubtargetPredicate = HasTrue16BitInsts in
1176+
let SubtargetPredicate = UseRealTrue16Insts in
11771177
defm : f16_fp_Pats<V_CVT_F16_F32_t16_e64, V_CVT_F32_F16_t16_e64>;
11781178

1179+
let SubtargetPredicate = UseFakeTrue16Insts in
1180+
defm : f16_fp_Pats<V_CVT_F16_F32_fake16_e64, V_CVT_F32_F16_fake16_e64>;
1181+
11791182
//===----------------------------------------------------------------------===//
11801183
// VOP2 Patterns
11811184
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td‎

Lines changed: 60 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -196,12 +196,20 @@ class VOPProfileI2F_True16<ValueType dstVt, ValueType srcVt> :
196196

197197
let HasModifiers = 0;
198198
let HasClamp = 1;
199+
200+
// this is a hack to avoid decoderNamespace issue
201+
let IsRealTrue16 = 1;
199202
}
200203

201204
def VOP1_F64_I32 : VOPProfileI2F <f64, i32>;
202205
def VOP1_F32_I32 : VOPProfileI2F <f32, i32>;
203206
def VOP1_F16_I16 : VOPProfileI2F <f16, i16>;
204207
def VOP1_F16_I16_t16 : VOPProfileI2F_True16 <f16, i16>;
208+
def VOP1_F16_I16_fake16 : VOPProfile_Fake16 <VOP_F16_I16> {
209+
let HasModifiers = 0;
210+
let HasOMod = 1;
211+
let HasClamp = 1;
212+
}
205213

206214
def VOP_NOP_PROFILE : VOPProfile <[untyped, untyped, untyped, untyped]>{
207215
let HasExtVOP3DPP = 0;
@@ -219,6 +227,12 @@ def VOP_I32_F64_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f64>;
219227
def VOP_I16_F16_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i16, f16>;
220228
def VOP_I16_F16_SPECIAL_OMOD_t16 : VOPProfile_Fake16<VOP_I16_F16> {
221229
let HasOMod = 1;
230+
231+
// this is a hack to avoid decoderNamespace issue
232+
let IsRealTrue16 = 1;
233+
}
234+
def VOP_I16_F16_SPECIAL_OMOD_fake16 : VOPProfile_Fake16<VOP_I16_F16> {
235+
let HasOMod = 1;
222236
}
223237

224238
//===----------------------------------------------------------------------===//
@@ -294,16 +308,22 @@ defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;
294308
defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_uint>;
295309
defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_sint>;
296310
let FPDPRounding = 1, isReMaterializable = 0 in {
311+
// V_CVT_F16_F32 and V_CVT_F32_F16 are a special case because they are
312+
// present in targets without Has16BitInsts. Otherwise they could use
313+
// class VOP1Inst_t16.
297314
let OtherPredicates = [NotHasTrue16BitInsts] in
298-
defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, any_fpround>;
299-
let OtherPredicates = [HasTrue16BitInsts] in
300-
defm V_CVT_F16_F32_t16 : VOP1Inst <"v_cvt_f16_f32_t16", VOPProfile_Fake16<VOP_F16_F32>, any_fpround>;
315+
defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, any_fpround>;
316+
let OtherPredicates = [UseRealTrue16Insts] in
317+
defm V_CVT_F16_F32_t16 : VOP1Inst <"v_cvt_f16_f32_t16", VOPProfileI2F_True16<f16, f32>, any_fpround>;
318+
let OtherPredicates = [UseFakeTrue16Insts] in
319+
defm V_CVT_F16_F32_fake16 : VOP1Inst <"v_cvt_f16_f32_fake16", VOPProfile_Fake16<VOP_F16_F32>, any_fpround>;
301320
} // End FPDPRounding = 1, isReMaterializable = 0
302-
303321
let OtherPredicates = [NotHasTrue16BitInsts] in
304-
defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, any_fpextend>;
305-
let OtherPredicates = [HasTrue16BitInsts] in
306-
defm V_CVT_F32_F16_t16 : VOP1Inst <"v_cvt_f32_f16_t16", VOPProfile_Fake16<VOP_F32_F16>, any_fpextend>;
322+
defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, any_fpextend>;
323+
let OtherPredicates = [UseRealTrue16Insts] in
324+
defm V_CVT_F32_F16_t16 : VOP1Inst <"v_cvt_f32_f16_t16", VOPProfileI2F_True16<f32, f16>, any_fpextend>;
325+
let OtherPredicates = [UseFakeTrue16Insts] in
326+
defm V_CVT_F32_F16_fake16 : VOP1Inst <"v_cvt_f32_f16_fake16", VOPProfile_Fake16<VOP_F32_F16>, any_fpextend>;
307327

308328
let ReadsModeReg = 0, mayRaiseFPException = 0 in {
309329
defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;
@@ -473,24 +493,15 @@ let SubtargetPredicate = isGFX7Plus in {
473493
} // End isReMaterializable = 1
474494

475495
let FPDPRounding = 1 in {
476-
let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
477-
defm V_CVT_F16_U16 : VOP1Inst <"v_cvt_f16_u16", VOP1_F16_I16, uint_to_fp>;
478-
defm V_CVT_F16_I16 : VOP1Inst <"v_cvt_f16_i16", VOP1_F16_I16, sint_to_fp>;
479-
}
480-
let OtherPredicates = [HasTrue16BitInsts] in {
481-
defm V_CVT_F16_U16_t16 : VOP1Inst <"v_cvt_f16_u16_t16", VOP1_F16_I16_t16, uint_to_fp>;
482-
defm V_CVT_F16_I16_t16 : VOP1Inst <"v_cvt_f16_i16_t16", VOP1_F16_I16_t16, sint_to_fp>;
483-
}
496+
defm V_CVT_F16_U16 : VOP1Inst_t16_with_profiles <"v_cvt_f16_u16", VOP1_F16_I16, VOP1_F16_I16_t16, VOP1_F16_I16_fake16, uint_to_fp>;
497+
defm V_CVT_F16_I16 : VOP1Inst_t16_with_profiles <"v_cvt_f16_i16", VOP1_F16_I16, VOP1_F16_I16_t16, VOP1_F16_I16_fake16, sint_to_fp>;
484498
} // End FPDPRounding = 1
485499
// OMod clears exceptions when set in these two instructions
486-
let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
487-
defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_uint>;
488-
defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_sint>;
489-
}
490-
let OtherPredicates = [HasTrue16BitInsts] in {
491-
defm V_CVT_U16_F16_t16 : VOP1Inst <"v_cvt_u16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16, fp_to_uint>;
492-
defm V_CVT_I16_F16_t16 : VOP1Inst <"v_cvt_i16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16, fp_to_sint>;
493-
}
500+
defm V_CVT_U16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_u16_f16",
501+
VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, fp_to_uint>;
502+
defm V_CVT_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_i16_f16",
503+
VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, fp_to_sint>;
504+
494505
let TRANS = 1, SchedRW = [WriteTrans32] in {
495506
defm V_RCP_F16 : VOP1Inst_t16 <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>;
496507
defm V_SQRT_F16 : VOP1Inst_t16 <"v_sqrt_f16", VOP_F16_F16, any_amdgcn_sqrt>;
@@ -501,12 +512,8 @@ defm V_SIN_F16 : VOP1Inst_t16 <"v_sin_f16", VOP_F16_F16, AMDGPUsin>;
501512
defm V_COS_F16 : VOP1Inst_t16 <"v_cos_f16", VOP_F16_F16, AMDGPUcos>;
502513
} // End TRANS = 1, SchedRW = [WriteTrans32]
503514
defm V_FREXP_MANT_F16 : VOP1Inst_t16 <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>;
504-
let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
505-
defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16_SPECIAL_OMOD, int_amdgcn_frexp_exp>;
506-
}
507-
let OtherPredicates = [HasTrue16BitInsts] in {
508-
defm V_FREXP_EXP_I16_F16_t16 : VOP1Inst <"v_frexp_exp_i16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16, int_amdgcn_frexp_exp>;
509-
}
515+
defm V_FREXP_EXP_I16_F16 : VOP1Inst_t16_with_profiles <"v_frexp_exp_i16_f16",
516+
VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, int_amdgcn_frexp_exp>;
510517
defm V_FLOOR_F16 : VOP1Inst_t16 <"v_floor_f16", VOP_F16_F16, ffloor>;
511518
defm V_CEIL_F16 : VOP1Inst_t16 <"v_ceil_f16", VOP_F16_F16, fceil>;
512519
defm V_TRUNC_F16 : VOP1Inst_t16 <"v_trunc_f16", VOP_F16_F16, ftrunc>;
@@ -525,7 +532,7 @@ def : GCNPat<
525532
(V_CVT_F16_F32_e32 $src)
526533
>;
527534
}
528-
let OtherPredicates = [HasTrue16BitInsts] in {
535+
let OtherPredicates = [UseRealTrue16Insts] in {
529536
def : GCNPat<
530537
(f32 (f16_to_fp i16:$src)),
531538
(V_CVT_F32_F16_t16_e32 $src)
@@ -535,6 +542,16 @@ def : GCNPat<
535542
(V_CVT_F16_F32_t16_e32 $src)
536543
>;
537544
}
545+
let OtherPredicates = [UseFakeTrue16Insts] in {
546+
def : GCNPat<
547+
(f32 (f16_to_fp i16:$src)),
548+
(V_CVT_F32_F16_fake16_e32 $src)
549+
>;
550+
def : GCNPat<
551+
(i16 (AMDGPUfp_to_f16 f32:$src)),
552+
(V_CVT_F16_F32_fake16_e32 $src)
553+
>;
554+
}
538555

539556
def VOP_SWAP_I32 : VOPProfile<[i32, i32, untyped, untyped]> {
540557
let Outs32 = (outs VGPR_32:$vdst, VRegSrc_32:$vdst1);
@@ -554,14 +571,10 @@ let SubtargetPredicate = isGFX9Plus in {
554571
defm V_SAT_PK_U8_I16 : VOP1Inst_t16<"v_sat_pk_u8_i16", VOP_I16_I32>;
555572

556573
let mayRaiseFPException = 0 in {
557-
let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
558-
defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16_SPECIAL_OMOD>;
559-
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16_SPECIAL_OMOD>;
560-
}
561-
let OtherPredicates = [HasTrue16BitInsts] in {
562-
defm V_CVT_NORM_I16_F16_t16 : VOP1Inst<"v_cvt_norm_i16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16>;
563-
defm V_CVT_NORM_U16_F16_t16 : VOP1Inst<"v_cvt_norm_u16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16>;
564-
}
574+
defm V_CVT_NORM_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_norm_i16_f16",
575+
VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>;
576+
defm V_CVT_NORM_U16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_norm_u16_f16",
577+
VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>;
565578
} // End mayRaiseFPException = 0
566579
} // End SubtargetPredicate = isGFX9Plus
567580

@@ -975,9 +988,13 @@ defm V_CVT_I32_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x06a, "v_cvt_i32_
975988
defm V_CVT_U32_U16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x06b, "v_cvt_u32_u16">;
976989

977990
defm V_CVT_F16_U16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x050, "v_cvt_f16_u16">;
991+
defm V_CVT_F16_U16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x050, "v_cvt_f16_u16">;
978992
defm V_CVT_F16_I16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x051, "v_cvt_f16_i16">;
993+
defm V_CVT_F16_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x051, "v_cvt_f16_i16">;
979994
defm V_CVT_U16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x052, "v_cvt_u16_f16">;
995+
defm V_CVT_U16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x052, "v_cvt_u16_f16">;
980996
defm V_CVT_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x053, "v_cvt_i16_f16">;
997+
defm V_CVT_I16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x053, "v_cvt_i16_f16">;
981998
defm V_RCP_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x054, "v_rcp_f16">;
982999
defm V_RCP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x054, "v_rcp_f16">;
9831000
defm V_SQRT_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x055, "v_sqrt_f16">;
@@ -990,6 +1007,7 @@ defm V_EXP_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16"
9901007
defm V_EXP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">;
9911008
defm V_FREXP_MANT_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x059, "v_frexp_mant_f16">;
9921009
defm V_FREXP_EXP_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05a, "v_frexp_exp_i16_f16">;
1010+
defm V_FREXP_EXP_I16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05a, "v_frexp_exp_i16_f16">;
9931011
defm V_FLOOR_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;
9941012
defm V_FLOOR_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;
9951013
defm V_CEIL_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16">;
@@ -1001,10 +1019,14 @@ defm V_SIN_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x060, "v_sin_f16"
10011019
defm V_COS_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x061, "v_cos_f16">;
10021020
defm V_SAT_PK_U8_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x062, "v_sat_pk_u8_i16">;
10031021
defm V_CVT_NORM_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;
1022+
defm V_CVT_NORM_I16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;
10041023
defm V_CVT_NORM_U16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x064, "v_cvt_norm_u16_f16">;
1024+
defm V_CVT_NORM_U16_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x064, "v_cvt_norm_u16_f16">;
10051025

10061026
defm V_CVT_F16_F32_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00a, "v_cvt_f16_f32">;
1027+
defm V_CVT_F16_F32_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00a, "v_cvt_f16_f32">;
10071028
defm V_CVT_F32_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00b, "v_cvt_f32_f16">;
1029+
defm V_CVT_F32_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x00b, "v_cvt_f32_f16">;
10081030

10091031
//===----------------------------------------------------------------------===//
10101032
// GFX10.

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