Skip to content

Commit 0b42e11

Browse files
[ProfCheck] Exclude some more tests
These tests are currently showing up as red on the buildbot. We have not gotten to any of these passes yet, so add them to the exclude list for now.
1 parent a247da4 commit 0b42e11

File tree

1 file changed

+4
-0
lines changed

1 file changed

+4
-0
lines changed

llvm/utils/profcheck-xfail.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@ CodeGen/Hexagon/loop-idiom/hexagon-memmove2.ll
7979
CodeGen/Hexagon/loop-idiom/memmove-rt-check.ll
8080
CodeGen/NVPTX/lower-ctor-dtor.ll
8181
CodeGen/PowerPC/P10-stack-alignment.ll
82+
CodeGen/WebAssembly/memory-interleave.ll
8283
CodeGen/X86/masked_gather_scatter.ll
8384
CodeGen/X86/nocfivalue.ll
8485
DebugInfo/AArch64/ir-outliner.ll
@@ -111,6 +112,7 @@ Instrumentation/AddressSanitizer/asan-funclet.ll
111112
Instrumentation/AddressSanitizer/asan-masked-load-store.ll
112113
Instrumentation/AddressSanitizer/asan-optimize-callbacks.ll
113114
Instrumentation/AddressSanitizer/asan-pass-second-run.ll
115+
Instrumentation/AddressSanitizer/asan-scalable-vector.ll
114116
Instrumentation/AddressSanitizer/asan-stack-safety.ll
115117
Instrumentation/AddressSanitizer/asan-struct-scalable.ll
116118
Instrumentation/AddressSanitizer/asan-vp-load-store.ll
@@ -1468,11 +1470,13 @@ Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
14681470
Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
14691471
Transforms/LoopVectorize/vplan-widen-call-instruction.ll
14701472
Transforms/LoopVectorize/vplan-widen-select-instruction.ll
1473+
Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
14711474
Transforms/LoopVectorize/X86/avx1.ll
14721475
Transforms/LoopVectorize/X86/avx512.ll
14731476
Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
14741477
Transforms/LoopVectorize/X86/constant-fold.ll
14751478
Transforms/LoopVectorize/X86/conversion-cost.ll
1479+
Transforms/LoopVectorize/X86/cost-conditional-branches.ll
14761480
Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
14771481
Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
14781482
Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll

0 commit comments

Comments
 (0)