@@ -79,11 +79,6 @@ static bool isVectorRegClass(Register R, const MachineRegisterInfo *MRI) {
79
79
80
80
// / Represents the EMUL and EEW of a MachineOperand.
81
81
struct OperandInfo {
82
- enum class State {
83
- Unknown,
84
- Known,
85
- } S;
86
-
87
82
// Represent as 1,2,4,8, ... and fractional indicator. This is because
88
83
// EMUL can take on values that don't map to RISCVII::VLMUL values exactly.
89
84
// For example, a mask operand can have an EMUL less than MF8.
@@ -92,41 +87,32 @@ struct OperandInfo {
92
87
unsigned Log2EEW;
93
88
94
89
OperandInfo (RISCVII::VLMUL EMUL, unsigned Log2EEW)
95
- : S(State::Known), EMUL(RISCVVType::decodeVLMUL(EMUL)), Log2EEW(Log2EEW) {
96
- }
90
+ : EMUL(RISCVVType::decodeVLMUL(EMUL)), Log2EEW(Log2EEW) {}
97
91
98
92
OperandInfo (std::pair<unsigned , bool > EMUL, unsigned Log2EEW)
99
- : S(State::Known), EMUL(EMUL), Log2EEW(Log2EEW) {}
100
-
101
- OperandInfo (unsigned Log2EEW) : S(State::Known), Log2EEW(Log2EEW) {}
93
+ : EMUL(EMUL), Log2EEW(Log2EEW) {}
102
94
103
- OperandInfo () : S(State::Unknown ) {}
95
+ OperandInfo (unsigned Log2EEW ) : Log2EEW(Log2EEW ) {}
104
96
105
- bool isUnknown () const { return S == State::Unknown; }
106
- bool isKnown () const { return S == State::Known; }
97
+ OperandInfo () = delete ;
107
98
108
99
static bool EMULAndEEWAreEqual (const OperandInfo &A, const OperandInfo &B) {
109
- assert (A.isKnown () && B.isKnown () && " Both operands must be known" );
110
-
111
100
return A.Log2EEW == B.Log2EEW && A.EMUL ->first == B.EMUL ->first &&
112
101
A.EMUL ->second == B.EMUL ->second ;
113
102
}
114
103
115
104
static bool EEWAreEqual (const OperandInfo &A, const OperandInfo &B) {
116
- assert (A.isKnown () && B.isKnown () && " Both operands must be known" );
117
105
return A.Log2EEW == B.Log2EEW ;
118
106
}
119
107
120
108
void print (raw_ostream &OS) const {
121
- if (isUnknown ()) {
122
- OS << " Unknown" ;
123
- return ;
124
- }
125
- assert (EMUL && " Expected EMUL to have value" );
126
- OS << " EMUL: m" ;
127
- if (EMUL->second )
128
- OS << " f" ;
129
- OS << EMUL->first ;
109
+ if (EMUL) {
110
+ OS << " EMUL: m" ;
111
+ if (EMUL->second )
112
+ OS << " f" ;
113
+ OS << EMUL->first ;
114
+ } else
115
+ OS << " EMUL: unknown\n " ;
130
116
OS << " , EEW: " << (1 << Log2EEW);
131
117
}
132
118
};
@@ -137,6 +123,16 @@ static raw_ostream &operator<<(raw_ostream &OS, const OperandInfo &OI) {
137
123
return OS;
138
124
}
139
125
126
+ LLVM_ATTRIBUTE_UNUSED
127
+ static raw_ostream &operator <<(raw_ostream &OS,
128
+ const std::optional<OperandInfo> &OI) {
129
+ if (OI)
130
+ OI->print (OS);
131
+ else
132
+ OS << " nullopt" ;
133
+ return OS;
134
+ }
135
+
140
136
namespace llvm {
141
137
namespace RISCVVType {
142
138
// / Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and
@@ -715,20 +711,20 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
715
711
}
716
712
717
713
default :
718
- return {} ;
714
+ return std::nullopt ;
719
715
}
720
716
}
721
717
722
- static OperandInfo getOperandInfo ( const MachineOperand &MO,
723
- const MachineRegisterInfo *MRI) {
718
+ static std::optional< OperandInfo>
719
+ getOperandInfo ( const MachineOperand &MO, const MachineRegisterInfo *MRI) {
724
720
const MachineInstr &MI = *MO.getParent ();
725
721
const RISCVVPseudosTable::PseudoInfo *RVV =
726
722
RISCVVPseudosTable::getPseudoInfo (MI.getOpcode ());
727
723
assert (RVV && " Could not find MI in PseudoTable" );
728
724
729
725
std::optional<unsigned > Log2EEW = getOperandLog2EEW (MO, MRI);
730
726
if (!Log2EEW)
731
- return {} ;
727
+ return std::nullopt ;
732
728
733
729
switch (RVV->BaseInstr ) {
734
730
// Vector Reduction Operations
@@ -1185,9 +1181,10 @@ std::optional<MachineOperand> RISCVVLOptimizer::checkUsers(MachineInstr &MI) {
1185
1181
return std::nullopt;
1186
1182
}
1187
1183
1188
- OperandInfo ConsumerInfo = getOperandInfo (UserOp, MRI);
1189
- OperandInfo ProducerInfo = getOperandInfo (MI.getOperand (0 ), MRI);
1190
- if (ConsumerInfo.isUnknown () || ProducerInfo.isUnknown ()) {
1184
+ std::optional<OperandInfo> ConsumerInfo = getOperandInfo (UserOp, MRI);
1185
+ std::optional<OperandInfo> ProducerInfo =
1186
+ getOperandInfo (MI.getOperand (0 ), MRI);
1187
+ if (!ConsumerInfo || !ProducerInfo) {
1191
1188
LLVM_DEBUG (dbgs () << " Abort due to unknown operand information.\n " );
1192
1189
LLVM_DEBUG (dbgs () << " ConsumerInfo is: " << ConsumerInfo << " \n " );
1193
1190
LLVM_DEBUG (dbgs () << " ProducerInfo is: " << ProducerInfo << " \n " );
@@ -1198,9 +1195,9 @@ std::optional<MachineOperand> RISCVVLOptimizer::checkUsers(MachineInstr &MI) {
1198
1195
// compatible. Otherwise, the EMUL *and* EEW must be compatible.
1199
1196
bool IsVectorOpUsedAsScalarOp = isVectorOpUsedAsScalarOp (UserOp);
1200
1197
if ((IsVectorOpUsedAsScalarOp &&
1201
- !OperandInfo::EEWAreEqual (ConsumerInfo, ProducerInfo)) ||
1198
+ !OperandInfo::EEWAreEqual (* ConsumerInfo, * ProducerInfo)) ||
1202
1199
(!IsVectorOpUsedAsScalarOp &&
1203
- !OperandInfo::EMULAndEEWAreEqual (ConsumerInfo, ProducerInfo))) {
1200
+ !OperandInfo::EMULAndEEWAreEqual (* ConsumerInfo, * ProducerInfo))) {
1204
1201
LLVM_DEBUG (
1205
1202
dbgs ()
1206
1203
<< " Abort due to incompatible information for EMUL or EEW.\n " );
0 commit comments