--Added support for the extension SPV_KHR_relaxed_extended_instruction

--Modified the SPIRVEmitNonSemanticDI.cpp file for forward referencing
--Modified the test files to reflect the changes made in SPIRVEmitNonSemanticDI.cpp.

Author: aadeshps-mcw

llvm/docs/SPIRVUsage.rst

@@ -245,6 +245,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
      - Adds execution mode and capability to enable maximal reconvergence.
    * - ``SPV_ALTERA_blocking_pipes``
      - Adds new pipe read and write functions that have blocking semantics instead of the non-blocking semantics of the existing pipe read/write functions.
+   * - `` SPV_KHR_relaxed_extended_instruction``
+     - Adds the ability to have forward declaration in some specific non-semantic instructions.
 
 SPIR-V representation in LLVM IR
 ================================

llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp

@@ -110,7 +110,7 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
     printOpDecorate(MI, OS);
   } else if (OpCode == SPIRV::OpExtInstImport) {
     recordOpExtInstImport(MI);
-  } else if (OpCode == SPIRV::OpExtInst) {
+  } else if (OpCode == SPIRV::OpExtInst || OpCode == SPIRV::OpExtInstWithForwardRefsKHR) {
     printOpExtInst(MI, OS);
   } else if (OpCode == SPIRV::UNKNOWN_type) {
     printUnknownType(MI, OS);

llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp

@@ -163,7 +163,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
         {"SPV_INTEL_kernel_attributes",
          SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes},
         {"SPV_ALTERA_blocking_pipes",
-         SPIRV::Extension::Extension::SPV_ALTERA_blocking_pipes}};
+         SPIRV::Extension::Extension::SPV_ALTERA_blocking_pipes},
+        {"SPV_KHR_relaxed_extended_instruction",
+         SPIRV::Extension::Extension::SPV_KHR_relaxed_extended_instruction}};
 
 bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
                                   StringRef ArgValue,

llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp

@@ -84,6 +84,8 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
 
   DenseMap<const Metadata *, Register> MDMap;
 
+  llvm::DenseSet<llvm::Register> PlaceholderRegs;
+
   // Maps OpVariable and OpFunction-related v-regs to its LLVM IR definition.
   DenseMap<std::pair<const MachineFunction *, Register>, const Value *> Reg2GO;
 
@@ -144,6 +146,18 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
 
   void addDebugValue(const Metadata *MD, Register Reg) { MDMap[MD] = Reg; }
 
+  void markAsForwardPlaceholder(llvm::Register Reg) {
+    PlaceholderRegs.insert(Reg);
+  }
+
+  bool isForwardPlaceholder(llvm::Register Reg) const {
+    return PlaceholderRegs.count(Reg);
+  }
+
+  void resolveForwardPlaceholder(llvm::Register Reg) {
+    PlaceholderRegs.erase(Reg);
+  }
+
   // A registry of "assign type" records:
   // - Add a record.
   void addAssignPtrTypeInstr(Value *Val, CallInst *AssignPtrTyCI) {

llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h

@@ -148,6 +148,8 @@ def OpExtInstImport: Op<11, (outs ID:$res), (ins StringImm:$extInstsName, variab
 // perspective of the instruction selection pass
 def OpExtInst: Op<12, (outs ID:$res), (ins TYPE:$ty, i32imm:$set, Extension:$inst, variable_ops),
                   "$res = OpExtInst $ty $set $inst">;
+def OpExtInstWithForwardRefsKHR: Op<4433, (outs ID:$res), (ins TYPE:$ty, i32imm:$set, Extension:$inst, variable_ops),
+                  "$res = OpExtInstWithForwardRefsKHR $ty $set $inst">;
 // 3.42.5 Mode-Setting Instructions
 
 def OpMemoryModel: Op<14, (outs), (ins AddressingModel:$addr, MemoryModel:$mem),

llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

@@ -56,7 +56,9 @@ void SPIRVMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI,
       break;
     }
     case MachineOperand::MO_Immediate:
-      if (MI->getOpcode() == SPIRV::OpExtInst && i == 2) {
+      if ((MI->getOpcode() == SPIRV::OpExtInst ||
+           MI->getOpcode() == SPIRV::OpExtInstWithForwardRefsKHR) &&
+          i == 2) {
         MCRegister Reg = MAI->getExtInstSetReg(MO.getImm());
         MCOp = MCOperand::createReg(Reg);
       } else {

llvm/lib/Target/SPIRV/SPIRVMCInstLower.cpp

@@ -647,7 +647,7 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
         const unsigned OpCode = MI.getOpcode();
         if (OpCode == SPIRV::OpString) {
           collectOtherInstr(MI, MAI, SPIRV::MB_DebugStrings, IS);
-        } else if (OpCode == SPIRV::OpExtInst && MI.getOperand(2).isImm() &&
+        } else if ((OpCode == SPIRV::OpExtInst|| OpCode == SPIRV::OpExtInstWithForwardRefsKHR) && MI.getOperand(2).isImm() &&
                    MI.getOperand(2).getImm() ==
                        SPIRV::InstructionSet::
                            NonSemantic_Shader_DebugInfo_100) {
@@ -2087,6 +2087,16 @@ void addInstrRequirements(const MachineInstr &MI,
         SPIRV::Capability::SubgroupMatrixMultiplyAccumulateINTEL);
     break;
   }
+  case SPIRV::OpExtInstWithForwardRefsKHR: {
+    if (!ST.canUseExtension(
+            SPIRV::Extension::SPV_KHR_relaxed_extended_instruction))
+      report_fatal_error("OpExtInstWithForwardRefsKHR instruction requires the "
+                         "following SPIR-V "
+                         "extension: SPV_KHR_relaxed_extended_instruction",
+                         false);
+    Reqs.addExtension(SPIRV::Extension::SPV_KHR_relaxed_extended_instruction);
+    break;
+  }
   case SPIRV::OpBitwiseFunctionINTEL: {
     if (!ST.canUseExtension(
             SPIRV::Extension::SPV_INTEL_ternary_bitwise_function))

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

@@ -390,6 +390,7 @@ defm SPV_KHR_maximal_reconvergence : ExtensionOperand<128, [EnvVulkan]>;
 defm SPV_INTEL_bfloat16_arithmetic
     : ExtensionOperand<129, [EnvVulkan, EnvOpenCL]>;
 defm SPV_INTEL_16bit_atomics : ExtensionOperand<130, [EnvVulkan, EnvOpenCL]>;
+defm SPV_KHR_relaxed_extended_instruction : ExtensionOperand<131, [EnvVulkan, EnvOpenCL]>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define Capabilities enum values and at the same time

llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td

@@ -6,7 +6,7 @@
 ; CHECK-MIR-DAG: [[type_void:%[0-9]+:type]] = OpTypeVoid
 ; CHECK-MIR-DAG: [[source:%[0-9]+:.*]] = OpExtInst [[type_void]], 3, 35, {{%[0-9]+:.*}}
 ; CHECK-MIR-DAG: [[compile_unit:%[0-9]+:.*]] = OpExtInst [[type_void]], 3, 1
-; CHECK-MIR-DAG: [[type_func:%[0-9]+:.*]] = OpExtInst [[type_void]], 3, 8, {{%[0-9]+:.*}}, [[type_void]]
+; CHECK-MIR-DAG: [[type_func:%[0-9]+:.*]] = OpExtInst [[type_void]], 3, 8
 ; CHECK-MIR-DAG: [[func1:%[0-9]+:.*]] = OpExtInst [[type_void]], 3, 20, {{%[0-9]+:.*}}, [[type_func]], [[source]], {{%[0-9]+:.*}}, {{%[0-9]+:.*}}, [[compile_unit]]
 ; CHECK-MIR-DAG: [[func2:%[0-9]+:.*]] = OpExtInst [[type_void]], 3, 20, {{%[0-9]+:.*}}, [[type_func]], [[source]], {{%[0-9]+:.*}}, {{%[0-9]+:.*}}, [[compile_unit]]
 
@@ -18,7 +18,7 @@
 ; CHECK-SPIRV: %[[#zero:]] = OpConstant %[[#Ty32]] 0
 ; CHECK-SPIRV: %[[#debug_source:]] = OpExtInst %[[#void]] %[[#ext_inst_non_semantic]] DebugSource
 ; CHECK-SPIRV: %[[#debug_compilation:]] = OpExtInst %[[#void]] %[[#ext_inst_non_semantic]] DebugCompilationUnit
-; CHECK-SPIRV: %[[#typefunc:]] = OpExtInst %[[#void]] %[[#ext_inst_non_semantic]] DebugTypeFunction %[[#zero]] %[[#void]]
+; CHECK-SPIRV: %[[#typefunc:]] = OpExtInst %[[#void]] %[[#ext_inst_non_semantic]] DebugTypeFunction %[[#zero]]
 ; CHECK-SPIRV: %[[#func1:]] = OpExtInst %[[#void]] %[[#ext_inst_non_semantic]] DebugFunction %[[#test1]] %[[#typefunc]] %[[#debug_source]] %[[#]] %[[#]] %[[#debug_compilation]]
 ; CHECK-SPIRV: %[[#func2:]] = OpExtInst %[[#void]] %[[#ext_inst_non_semantic]] DebugFunction %[[#test2]] %[[#typefunc]] %[[#debug_source]] %[[#]] %[[#]] %[[#debug_compilation]]