Skip to content

Commit 0c04d43

Browse files
dlav-scdlav-sc
authored
[RISCV][NFC] refactor CFI emitting (#114227)
This patch refactor PR #110810 to remove code duplication.
1 parent 4e7682b commit 0c04d43

File tree

2 files changed

+88
-69
lines changed

2 files changed

+88
-69
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp‎

Lines changed: 85 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,64 @@
2727

2828
using namespace llvm;
2929

30+
namespace {
31+
32+
class CFISaveRegisterEmitter {
33+
MachineFunction &MF;
34+
MachineFrameInfo &MFI;
35+
36+
public:
37+
CFISaveRegisterEmitter(MachineFunction &MF)
38+
: MF{MF}, MFI{MF.getFrameInfo()} {};
39+
40+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
41+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
42+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
43+
int FrameIdx = CS.getFrameIdx();
44+
int64_t Offset = MFI.getObjectOffset(FrameIdx);
45+
Register Reg = CS.getReg();
46+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
47+
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
48+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
49+
.addCFIIndex(CFIIndex)
50+
.setMIFlag(MachineInstr::FrameSetup);
51+
}
52+
};
53+
54+
class CFIRestoreRegisterEmitter {
55+
MachineFunction &MF;
56+
57+
public:
58+
CFIRestoreRegisterEmitter(MachineFunction &MF) : MF{MF} {};
59+
60+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
61+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
62+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
63+
Register Reg = CS.getReg();
64+
unsigned CFIIndex = MF.addFrameInst(
65+
MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
66+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
67+
.addCFIIndex(CFIIndex)
68+
.setMIFlag(MachineInstr::FrameDestroy);
69+
}
70+
};
71+
72+
} // namespace
73+
74+
template <typename Emitter>
75+
void RISCVFrameLowering::emitCFIForCSI(
76+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
77+
const SmallVector<CalleeSavedInfo, 8> &CSI) const {
78+
MachineFunction *MF = MBB.getParent();
79+
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
80+
const RISCVInstrInfo *TII = STI.getInstrInfo();
81+
DebugLoc DL = MBB.findDebugLoc(MBBI);
82+
83+
Emitter E{*MF};
84+
for (const auto &CS : CSI)
85+
E.emit(MBB, MBBI, *RI, *TII, DL, CS);
86+
}
87+
3088
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
3189
if (ABI == RISCVABI::ABI_ILP32E)
3290
return Align(4);
@@ -426,18 +484,18 @@ getPushOrLibCallsSavedInfo(const MachineFunction &MF,
426484
const std::vector<CalleeSavedInfo> &CSI) {
427485
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
428486

429-
SmallVector<CalleeSavedInfo, 8> PushPopOrLibCallsCSI;
487+
SmallVector<CalleeSavedInfo, 8> PushOrLibCallsCSI;
430488
if (!RVFI->useSaveRestoreLibCalls(MF) && !RVFI->isPushable(MF))
431-
return PushPopOrLibCallsCSI;
489+
return PushOrLibCallsCSI;
432490

433-
for (auto &CS : CSI) {
491+
for (const auto &CS : CSI) {
434492
const auto *FII = llvm::find_if(
435493
FixedCSRFIMap, [&](auto P) { return P.first == CS.getReg(); });
436494
if (FII != std::end(FixedCSRFIMap))
437-
PushPopOrLibCallsCSI.push_back(CS);
495+
PushOrLibCallsCSI.push_back(CS);
438496
}
439497

440-
return PushPopOrLibCallsCSI;
498+
return PushOrLibCallsCSI;
441499
}
442500

443501
void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
@@ -618,16 +676,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
618676
.addCFIIndex(CFIIndex)
619677
.setMIFlag(MachineInstr::FrameSetup);
620678

621-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
622-
int FrameIdx = Entry.getFrameIdx();
623-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
624-
Register Reg = Entry.getReg();
625-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
626-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
627-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
628-
.addCFIIndex(CFIIndex)
629-
.setMIFlag(MachineInstr::FrameSetup);
630-
}
679+
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI,
680+
getPushOrLibCallsSavedInfo(MF, CSI));
631681
}
632682

633683
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
@@ -659,7 +709,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
659709
// stack space. Align the stack size down to a multiple of 16. This is
660710
// needed for RVE.
661711
// FIXME: Can we increase the stack size to a multiple of 16 instead?
662-
uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
712+
uint64_t Spimm =
713+
std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
663714
FirstFrameSetup->getOperand(1).setImm(Spimm);
664715
StackSize -= Spimm;
665716

@@ -669,16 +720,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
669720
.addCFIIndex(CFIIndex)
670721
.setMIFlag(MachineInstr::FrameSetup);
671722

672-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
673-
int FrameIdx = Entry.getFrameIdx();
674-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
675-
Register Reg = Entry.getReg();
676-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
677-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
678-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
679-
.addCFIIndex(CFIIndex)
680-
.setMIFlag(MachineInstr::FrameSetup);
681-
}
723+
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI,
724+
getPushOrLibCallsSavedInfo(MF, CSI));
682725
}
683726

684727
if (StackSize != 0) {
@@ -705,20 +748,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
705748

706749
// Iterate over list of callee-saved registers and emit .cfi_offset
707750
// directives.
708-
for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
709-
int FrameIdx = Entry.getFrameIdx();
710-
if (FrameIdx >= 0 &&
711-
MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
712-
continue;
713-
714-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
715-
Register Reg = Entry.getReg();
716-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
717-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
718-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
719-
.addCFIIndex(CFIIndex)
720-
.setMIFlag(MachineInstr::FrameSetup);
721-
}
751+
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
722752

723753
// Generate new FP.
724754
if (hasFP(MF)) {
@@ -966,14 +996,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
966996
}
967997

968998
// Recover callee-saved registers.
969-
for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
970-
Register Reg = Entry.getReg();
971-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
972-
nullptr, RI->getDwarfRegNum(Reg, true)));
973-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
974-
.addCFIIndex(CFIIndex)
975-
.setMIFlag(MachineInstr::FrameDestroy);
976-
}
999+
emitCFIForCSI<CFIRestoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
9771000

9781001
bool ApplyPop = RVFI->isPushable(MF) && MBBI != MBB.end() &&
9791002
MBBI->getOpcode() == RISCV::CM_POP;
@@ -982,7 +1005,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9821005
// space. Align the stack size down to a multiple of 16. This is needed for
9831006
// RVE.
9841007
// FIXME: Can we increase the stack size to a multiple of 16 instead?
985-
uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
1008+
uint64_t Spimm =
1009+
std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
9861010
MBBI->getOperand(1).setImm(Spimm);
9871011
StackSize -= Spimm;
9881012

@@ -994,14 +1018,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9941018
if (NextI == MBB.end() || NextI->getOpcode() != RISCV::PseudoRET) {
9951019
++MBBI;
9961020

997-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
998-
Register Reg = Entry.getReg();
999-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
1000-
nullptr, RI->getDwarfRegNum(Reg, true)));
1001-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1002-
.addCFIIndex(CFIIndex)
1003-
.setMIFlag(MachineInstr::FrameDestroy);
1004-
}
1021+
emitCFIForCSI<CFIRestoreRegisterEmitter>(
1022+
MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI));
10051023

10061024
// Update CFA offset. After CM_POP SP should be equal to CFA, so CFA
10071025
// offset should be a zero.
@@ -1701,7 +1719,7 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
17011719
return true;
17021720
}
17031721

1704-
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
1722+
static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) {
17051723
return RISCV::VRRegClass.contains(BaseReg) ? 1
17061724
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
17071725
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
@@ -1743,16 +1761,14 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17431761
for (auto &CS : RVVCSI) {
17441762
// Insert the spill to the stack frame.
17451763
int FI = CS.getFrameIdx();
1746-
if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector) {
1747-
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1748-
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
1749-
for (unsigned i = 0; i < NumRegs; ++i) {
1750-
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1751-
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
1752-
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1753-
.addCFIIndex(CFIIndex)
1754-
.setMIFlag(MachineInstr::FrameSetup);
1755-
}
1764+
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1765+
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
1766+
for (unsigned i = 0; i < NumRegs; ++i) {
1767+
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1768+
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
1769+
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1770+
.addCFIIndex(CFIIndex)
1771+
.setMIFlag(MachineInstr::FrameSetup);
17561772
}
17571773
}
17581774
}
@@ -1769,7 +1785,7 @@ void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
17691785
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
17701786
for (auto &CS : RVVCSI) {
17711787
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1772-
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
1788+
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
17731789
for (unsigned i = 0; i < NumRegs; ++i) {
17741790
unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
17751791
nullptr, RI->getDwarfRegNum(BaseReg + i, true)));

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,9 @@ class RISCVFrameLowering : public TargetFrameLowering {
9393
bool HasFP) const;
9494
void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
9595
MachineBasicBlock::iterator MI) const;
96+
template <typename Emitter>
97+
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
98+
const SmallVector<CalleeSavedInfo, 8> &CSI) const;
9699
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
97100
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
98101
uint64_t &StackSize, int64_t CFAOffset) const;

0 commit comments

Comments
 (0)