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Remove driveby formatting fixes
1 parent ba96d63 commit 0c3ddc5

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3 files changed

+6
-9
lines changed

3 files changed

+6
-9
lines changed

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4315,7 +4315,6 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
43154315
return DAG.getNode(ISD::BITCAST, SL, VT, Vec);
43164316
}
43174317

4318-
43194318
SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
43204319
DAGCombinerInfo &DCI) const {
43214320
SDValue RHS = N->getOperand(1);
@@ -4842,8 +4841,8 @@ AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
48424841
if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))
48434842
return SDValue();
48444843

4845-
return distributeOpThroughSelect(DCI, LHS.getOpcode(), SDLoc(N), Cond, LHS,
4846-
RHS);
4844+
return distributeOpThroughSelect(DCI, LHS.getOpcode(),
4845+
SDLoc(N), Cond, LHS,RHS);
48474846
}
48484847

48494848
bool Inv = false;

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13383,8 +13383,6 @@ SDValue SITargetLowering::performXorCombine(SDNode *N,
1338313383
return XSelect;
1338413384
}
1338513385

13386-
13387-
1338813386
// Make sure to apply the 64-bit constant splitting fold before trying to fold
1338913387
// fneg-like xors into 64-bit select.
1339013388
if (LHS.getOpcode() == ISD::SELECT && VT == MVT::i32) {
@@ -14430,10 +14428,9 @@ SITargetLowering::performExtractVectorEltCombine(SDNode *N,
1443014428
if (!DCI.isBeforeLegalize())
1443114429
return SDValue();
1443214430

14433-
// Try to turn sub-dword accesses of vectors into accesses of the same
14434-
// 32-bit elements. This exposes more load reduction opportunities by
14435-
// replacing multiple small extract_vector_elements with a single 32-bit
14436-
// extract.
14431+
// Try to turn sub-dword accesses of vectors into accesses of the same 32-bit
14432+
// elements. This exposes more load reduction opportunities by replacing
14433+
// multiple small extract_vector_elements with a single 32-bit extract.
1443714434
auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
1443814435
if (isa<MemSDNode>(Vec) && VecEltSize <= 16 && VecEltVT.isByteSized() &&
1443914436
VecSize > 32 && VecSize % 32 == 0 && Idx) {

llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1903,6 +1903,7 @@ def : GCNPat <
19031903
>;
19041904
}
19051905

1906+
19061907
/********** ================================ **********/
19071908
/********** Floating point absolute/negative **********/
19081909
/********** ================================ **********/

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