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fhahnfhahn
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!fixup update on top of current main, iterate to find vector.ph
1 parent 98529f3 commit 0c76e9d

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8 files changed

+68
-54
lines changed

8 files changed

+68
-54
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2406,12 +2406,12 @@ void InnerLoopVectorizer::scalarizeInstruction(const Instruction *Instr,
24062406
// End if-block.
24072407
VPRegionBlock *Parent = RepRecipe->getParent()->getParent();
24082408
bool IfPredicateInstr = Parent ? Parent->isReplicator() : false;
2409-
assert((Parent || all_of(RepRecipe->operands(),
2410-
[](VPValue *Op) {
2411-
return Op->isDefinedOutsideLoopRegions();
2412-
})) &&
2413-
"Expected a recipe is either within a region or all of its operands "
2414-
"are defined outside the vectorized region.");
2409+
assert(
2410+
(Parent || !RepRecipe->getParent()->getPlan()->getVectorLoopRegion() ||
2411+
all_of(RepRecipe->operands(),
2412+
[](VPValue *Op) { return Op->isDefinedOutsideLoopRegions(); })) &&
2413+
"Expected a recipe is either within a region or all of its operands "
2414+
"are defined outside the vectorized region.");
24152415
if (IfPredicateInstr)
24162416
PredicatedInstructions.push_back(Cloned);
24172417
}

‎llvm/lib/Transforms/Vectorize/VPlan.cpp‎

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1081,19 +1081,28 @@ InstructionCost VPlan::cost(ElementCount VF, VPCostContext &Ctx) {
10811081
return getVectorLoopRegion()->cost(VF, Ctx);
10821082
}
10831083

1084+
VPBasicBlock *VPlan::getVectorPreheader() {
1085+
VPBlockBase *Current = getEntry()->getSuccessors().back();
1086+
while (Current->getNumSuccessors() == 2)
1087+
Current = Current->getSuccessors().back();
1088+
return cast<VPBasicBlock>(Current);
1089+
}
1090+
1091+
VPBasicBlock *VPlan::getVectorPreheader() const {
1092+
VPBlockBase *Current = getEntry()->getSuccessors().back();
1093+
while (Current->getNumSuccessors() == 2)
1094+
Current = Current->getSuccessors().back();
1095+
return cast<VPBasicBlock>(Current);
1096+
}
1097+
10841098
VPRegionBlock *VPlan::getVectorLoopRegion() {
10851099
// TODO: Cache if possible.
1086-
for (VPBlockBase *B : vp_depth_first_shallow(getEntry()))
1087-
if (auto *R = dyn_cast<VPRegionBlock>(B))
1088-
return R;
1089-
return nullptr;
1100+
return dyn_cast<VPRegionBlock>(getVectorPreheader()->getSingleSuccessor());
1101+
;
10901102
}
10911103

10921104
const VPRegionBlock *VPlan::getVectorLoopRegion() const {
1093-
for (const VPBlockBase *B : vp_depth_first_shallow(getEntry()))
1094-
if (auto *R = dyn_cast<VPRegionBlock>(B))
1095-
return R;
1096-
return nullptr;
1105+
return dyn_cast<VPRegionBlock>(getVectorPreheader()->getSingleSuccessor());
10971106
}
10981107

10991108
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
@@ -1415,8 +1424,10 @@ void VPlanIngredient::print(raw_ostream &O) const {
14151424
#endif
14161425

14171426
bool VPValue::isDefinedOutsideLoopRegions() const {
1427+
14181428
return !hasDefiningRecipe() ||
1419-
!getDefiningRecipe()->getParent()->getEnclosingLoopRegion();
1429+
(!getDefiningRecipe()->getParent()->getEnclosingLoopRegion() &&
1430+
getDefiningRecipe()->getParent()->getPlan()->getVectorLoopRegion());
14201431
}
14211432

14221433
void VPValue::replaceAllUsesWith(VPValue *New) {

‎llvm/lib/Transforms/Vectorize/VPlan.h‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3869,12 +3869,8 @@ class VPlan {
38693869
const VPBasicBlock *getEntry() const { return Entry; }
38703870

38713871
/// Returns the preheader of the vector loop region.
3872-
VPBasicBlock *getVectorPreheader() {
3873-
auto *LoopRegion = getVectorLoopRegion();
3874-
if (!LoopRegion)
3875-
return nullptr;
3876-
return dyn_cast<VPBasicBlock>(LoopRegion->getSinglePredecessor());
3877-
}
3872+
VPBasicBlock *getVectorPreheader();
3873+
VPBasicBlock *getVectorPreheader() const;
38783874

38793875
/// Returns the VPRegionBlock of the vector loop.
38803876
VPRegionBlock *getVectorLoopRegion();

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -718,6 +718,11 @@ void VPlanTransforms::optimizeForVFAndUF(VPlan &Plan, ElementCount BestVF,
718718

719719
Header->setParent(nullptr);
720720
Exiting->setParent(nullptr);
721+
722+
for (VPBlockBase *B : vp_depth_first_shallow(LoopRegion->getEntry())) {
723+
if (isa<VPRegionBlock>(B))
724+
B->setParent(nullptr);
725+
}
721726
VPBlockUtils::connectBlocks(Preheader, Header);
722727

723728
VPBlockUtils::connectBlocks(Exiting, Middle);

‎llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -163,12 +163,12 @@ define void @truncate_to_i1_used_by_branch(i8 %x, ptr %dst) #0 {
163163
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i8> [[BROADCAST_SPLATINSERT]], <2 x i8> poison, <2 x i32> zeroinitializer
164164
; CHECK-NEXT: [[TMP0:%.*]] = trunc <2 x i8> [[BROADCAST_SPLAT]] to <2 x i1>
165165
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i1> splat (i1 true), [[TMP0]]
166+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <2 x ptr> poison, ptr [[DST]], i64 0
167+
; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <2 x ptr> [[BROADCAST_SPLATINSERT3]], <2 x ptr> poison, <2 x i32> zeroinitializer
166168
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
167169
; CHECK: [[VECTOR_BODY]]:
168170
; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 0, i32 2)
169171
; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[ACTIVE_LANE_MASK]], <2 x i1> [[TMP2]], <2 x i1> zeroinitializer
170-
; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <2 x ptr> poison, ptr [[DST]], i64 0
171-
; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <2 x ptr> [[BROADCAST_SPLATINSERT3]], <2 x ptr> poison, <2 x i32> zeroinitializer
172172
; CHECK-NEXT: call void @llvm.masked.scatter.v2i8.v2p0(<2 x i8> zeroinitializer, <2 x ptr> [[BROADCAST_SPLAT4]], i32 1, <2 x i1> [[TMP3]])
173173
; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]
174174
; CHECK: [[MIDDLE_BLOCK]]:

‎llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -27,91 +27,91 @@ define void @test(ptr %p, i40 %a) {
2727
; CHECK: pred.store.continue:
2828
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]]
2929
; CHECK: pred.store.if1:
30-
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
30+
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP8]], i32 1
3131
; CHECK-NEXT: store i1 [[TMP9]], ptr [[P]], align 1
3232
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]]
3333
; CHECK: pred.store.continue2:
3434
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
3535
; CHECK: pred.store.if3:
36-
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
36+
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP8]], i32 2
3737
; CHECK-NEXT: store i1 [[TMP12]], ptr [[P]], align 1
3838
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
3939
; CHECK: pred.store.continue4:
4040
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
4141
; CHECK: pred.store.if5:
42-
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
42+
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP8]], i32 3
4343
; CHECK-NEXT: store i1 [[TMP14]], ptr [[P]], align 1
4444
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
4545
; CHECK: pred.store.continue6:
4646
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
4747
; CHECK: pred.store.if7:
48-
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
48+
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP8]], i32 4
4949
; CHECK-NEXT: store i1 [[TMP16]], ptr [[P]], align 1
5050
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
5151
; CHECK: pred.store.continue8:
5252
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]]
5353
; CHECK: pred.store.if9:
54-
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
54+
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i1> [[TMP8]], i32 5
5555
; CHECK-NEXT: store i1 [[TMP18]], ptr [[P]], align 1
5656
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]]
5757
; CHECK: pred.store.continue10:
5858
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12:%.*]]
5959
; CHECK: pred.store.if11:
60-
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
60+
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <16 x i1> [[TMP8]], i32 6
6161
; CHECK-NEXT: store i1 [[TMP20]], ptr [[P]], align 1
6262
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE12]]
6363
; CHECK: pred.store.continue12:
6464
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE14:%.*]]
6565
; CHECK: pred.store.if13:
66-
; CHECK-NEXT: [[TMP22:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
66+
; CHECK-NEXT: [[TMP22:%.*]] = extractelement <16 x i1> [[TMP8]], i32 7
6767
; CHECK-NEXT: store i1 [[TMP22]], ptr [[P]], align 1
6868
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE14]]
6969
; CHECK: pred.store.continue14:
7070
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF15:%.*]], label [[PRED_STORE_CONTINUE16:%.*]]
7171
; CHECK: pred.store.if15:
72-
; CHECK-NEXT: [[TMP24:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
72+
; CHECK-NEXT: [[TMP24:%.*]] = extractelement <16 x i1> [[TMP8]], i32 8
7373
; CHECK-NEXT: store i1 [[TMP24]], ptr [[P]], align 1
7474
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE16]]
7575
; CHECK: pred.store.continue16:
7676
; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF17:%.*]], label [[PRED_STORE_CONTINUE18:%.*]]
7777
; CHECK: pred.store.if17:
78-
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
78+
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <16 x i1> [[TMP8]], i32 9
7979
; CHECK-NEXT: store i1 [[TMP26]], ptr [[P]], align 1
8080
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE18]]
8181
; CHECK: pred.store.continue18:
8282
; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF19:%.*]], label [[PRED_STORE_CONTINUE20:%.*]]
8383
; CHECK: pred.store.if19:
84-
; CHECK-NEXT: [[TMP28:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
84+
; CHECK-NEXT: [[TMP28:%.*]] = extractelement <16 x i1> [[TMP8]], i32 10
8585
; CHECK-NEXT: store i1 [[TMP28]], ptr [[P]], align 1
8686
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE20]]
8787
; CHECK: pred.store.continue20:
8888
; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF21:%.*]], label [[PRED_STORE_CONTINUE22:%.*]]
8989
; CHECK: pred.store.if21:
90-
; CHECK-NEXT: [[TMP30:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
90+
; CHECK-NEXT: [[TMP30:%.*]] = extractelement <16 x i1> [[TMP8]], i32 11
9191
; CHECK-NEXT: store i1 [[TMP30]], ptr [[P]], align 1
9292
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE22]]
9393
; CHECK: pred.store.continue22:
9494
; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF23:%.*]], label [[PRED_STORE_CONTINUE24:%.*]]
9595
; CHECK: pred.store.if23:
96-
; CHECK-NEXT: [[TMP32:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
96+
; CHECK-NEXT: [[TMP32:%.*]] = extractelement <16 x i1> [[TMP8]], i32 12
9797
; CHECK-NEXT: store i1 [[TMP32]], ptr [[P]], align 1
9898
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE24]]
9999
; CHECK: pred.store.continue24:
100100
; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF25:%.*]], label [[PRED_STORE_CONTINUE26:%.*]]
101101
; CHECK: pred.store.if25:
102-
; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
102+
; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x i1> [[TMP8]], i32 13
103103
; CHECK-NEXT: store i1 [[TMP34]], ptr [[P]], align 1
104104
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE26]]
105105
; CHECK: pred.store.continue26:
106106
; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF27:%.*]], label [[PRED_STORE_CONTINUE28:%.*]]
107107
; CHECK: pred.store.if27:
108-
; CHECK-NEXT: [[TMP36:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
108+
; CHECK-NEXT: [[TMP36:%.*]] = extractelement <16 x i1> [[TMP8]], i32 14
109109
; CHECK-NEXT: store i1 [[TMP36]], ptr [[P]], align 1
110110
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE28]]
111111
; CHECK: pred.store.continue28:
112112
; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF29:%.*]], label [[PRED_STORE_CONTINUE30:%.*]]
113113
; CHECK: pred.store.if29:
114-
; CHECK-NEXT: [[TMP38:%.*]] = extractelement <16 x i1> [[TMP8]], i32 0
114+
; CHECK-NEXT: [[TMP38:%.*]] = extractelement <16 x i1> [[TMP8]], i32 15
115115
; CHECK-NEXT: store i1 [[TMP38]], ptr [[P]], align 1
116116
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE30]]
117117
; CHECK: pred.store.continue30:

‎llvm/test/Transforms/LoopVectorize/SystemZ/scalar-steps-with-users-demanding-all-lanes-and-first-lane-only.ll‎

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -16,20 +16,22 @@ define void @test_scalar_iv_steps_used_by_replicate_and_first_lane_only_vpinst(p
1616
; CHECK: [[VECTOR_PH]]:
1717
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
1818
; CHECK: [[VECTOR_BODY]]:
19-
; CHECK-NEXT: [[TMP4:%.*]] = mul nsw i64 0, 4
20-
; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i64 0, 4
21-
; CHECK-NEXT: [[TMP2:%.*]] = mul nsw i64 0, 4
2219
; CHECK-NEXT: [[TMP3:%.*]] = mul nsw i64 0, 4
23-
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[SRC_1]], i64 [[TMP4]]
20+
; CHECK-NEXT: [[TMP4:%.*]] = mul nsw i64 1, 4
21+
; CHECK-NEXT: [[TMP2:%.*]] = mul nsw i64 2, 4
22+
; CHECK-NEXT: [[TMP15:%.*]] = mul nsw i64 3, 4
23+
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[SRC_1]], i64 [[TMP3]]
2424
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[SRC_1]], i64 [[TMP4]]
25-
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[SRC_1]], i64 [[TMP4]]
26-
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC_1]], i64 [[TMP4]]
25+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[SRC_1]], i64 [[TMP2]]
26+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC_1]], i64 [[TMP15]]
2727
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP8]], align 1
28-
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[TMP12]], i64 0
29-
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer
30-
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
31-
; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP8]], align 1
32-
; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP8]], align 1
28+
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP5]], align 1
29+
; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP6]], align 1
30+
; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP7]], align 1
31+
; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i8> poison, i8 [[TMP12]], i32 0
32+
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i8> [[TMP16]], i8 [[TMP9]], i32 1
33+
; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> [[TMP13]], i8 [[TMP10]], i32 2
34+
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> [[TMP14]], i8 [[TMP11]], i32 3
3335
; CHECK-NEXT: [[TMP20:%.*]] = icmp eq <4 x i8> [[TMP19]], zeroinitializer
3436
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr [8 x i32], ptr @src, i64 0, i64 4
3537
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP22]], i32 0
@@ -44,21 +46,21 @@ define void @test_scalar_iv_steps_used_by_replicate_and_first_lane_only_vpinst(p
4446
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP20]], i32 1
4547
; CHECK-NEXT: br i1 [[TMP26]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
4648
; CHECK: [[PRED_STORE_IF1]]:
47-
; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 0
49+
; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 1
4850
; CHECK-NEXT: store i32 [[TMP27]], ptr [[DST]], align 4
4951
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
5052
; CHECK: [[PRED_STORE_CONTINUE2]]:
5153
; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x i1> [[TMP20]], i32 2
5254
; CHECK-NEXT: br i1 [[TMP28]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
5355
; CHECK: [[PRED_STORE_IF3]]:
54-
; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 0
56+
; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 2
5557
; CHECK-NEXT: store i32 [[TMP29]], ptr [[DST]], align 4
5658
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
5759
; CHECK: [[PRED_STORE_CONTINUE4]]:
5860
; CHECK-NEXT: [[TMP30:%.*]] = extractelement <4 x i1> [[TMP20]], i32 3
5961
; CHECK-NEXT: br i1 [[TMP30]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
6062
; CHECK: [[PRED_STORE_IF5]]:
61-
; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 0
63+
; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 3
6264
; CHECK-NEXT: store i32 [[TMP31]], ptr [[DST]], align 4
6365
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
6466
; CHECK: [[PRED_STORE_CONTINUE6]]:

‎llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ define void @test_tc_less_than_16(ptr %A, i64 %N) {
7070
; CHECK-NEXT: IR %n.vec = sub i64 %and, %n.mod.vf
7171
; CHECK-NEXT: IR %ind.end = sub i64 %and, %n.vec
7272
; CHECK-NEXT: IR %ind.end1 = getelementptr i8, ptr %A, i64 %n.vec
73-
; CHECK-NEXT: Successor(s): vector loop
73+
; CHECK-NEXT: Successor(s): vector.body
7474
; CHECK-EMPTY:
7575
; CHECK-NEXT: vector.body:
7676
; CHECK-NEXT: vp<[[STEPS1:%.+]]> = SCALAR-STEPS ir<0>, ir<1>
@@ -85,7 +85,7 @@ define void @test_tc_less_than_16(ptr %A, i64 %N) {
8585
; CHECK-NEXT: vp<[[VPTR4:%.+]]> = vector-pointer vp<[[PADD1]]>, ir<1>
8686
; CHECK-NEXT: WIDEN store vp<[[VPTR3]]>, ir<%add>
8787
; CHECK-NEXT: WIDEN store vp<[[VPTR4]]>, ir<%add>.1
88-
; CHECK-NEXT: Successor(s): middle.block
88+
; CHECK-NEXT: Successor(s): ir-bb<middle.block>
8989
; CHECK-EMPTY:
9090
; CHECK-NEXT: ir-bb<middle.block>:
9191
; CHECK-NEXT: EMIT vp<[[C:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VTC]]>

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