Remove unused code

Author: HolyMolyCowMan

llvm/lib/Target/AArch64/AArch64Combine.td

@@ -332,13 +332,6 @@ def combine_mul_cmlt : GICombineRule<
   (apply [{ applyCombineMulCMLT(*${root}, MRI, B, ${matchinfo}); }])
 >;
 
-// def lower_fptrunc_fptrunc: GICombineRule<
-//   (defs root:$root),
-//   (match (wip_match_opcode G_FPTRUNC):$root,
-//         [{ return matchFpTruncFpTrunc(*${root}, MRI); }]),
-//   (apply [{ applyFpTruncFpTrunc(*${root}, MRI, B); }])
-// >;
-
 // Post-legalization combines which should happen at all optimization levels.
 // (E.g. ones that facilitate matching for the selector) For example, matching
 // pseudos.

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -901,198 +901,6 @@ unsigned getCmpOperandFoldingProfit(Register CmpOp, MachineRegisterInfo &MRI) {
   return 0;
 }
 
-// Helper function for matchFpTruncFpTrunc.
-// Checks that the given definition belongs to an FPTRUNC and that the source is
-// not an integer, as no rounding is necessary due to the range of values
-bool isFPTruncFromDouble(MachineRegisterInfo &MRI, MachineInstr *MaybeFpTrunc) {
-  if (!MaybeFpTrunc || MaybeFpTrunc->getOpcode() != TargetOpcode::G_FPTRUNC_ODD)
-    return false;
-
-  // Check the source is 64 bits as we only want to match a very specific
-  // pattern
-  Register FpTruncSrc = MaybeFpTrunc->getOperand(1).getReg();
-  LLT SrcTy = MRI.getType(FpTruncSrc);
-  if (SrcTy.getScalarSizeInBits() != 64)
-    return false;
-
-  // Need to check the float didn't come from an int as no rounding is
-  // neccessary
-  MachineInstr *FpTruncSrcDef = getDefIgnoringCopies(FpTruncSrc, MRI);
-  if (FpTruncSrcDef->getOpcode() == TargetOpcode::G_SITOFP ||
-      FpTruncSrcDef->getOpcode() == TargetOpcode::G_UITOFP)
-    return false;
-
-  return true;
-}
-
-// To avoid double rounding issues we need to lower FPTRUNC(FPTRUNC) to an odd
-// rounding truncate and a normal truncate. When
-// truncating an FP that came from an integer this is not a problem as the range
-// of values is lower in the int
-bool matchFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI) {
-  assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC && "Expected G_FPTRUNC");
-
-  // Check the destination is 16 bits as we only want to match a very specific
-  // pattern
-  Register Dst = MI.getOperand(0).getReg();
-  LLT DstTy = MRI.getType(Dst);
-  if (DstTy.getScalarSizeInBits() != 16)
-    return false;
-
-  Register Src = MI.getOperand(1).getReg();
-
-  MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
-  if (!ParentDef)
-    return false;
-
-  MachineInstr *FpTruncDef;
-  switch (ParentDef->getOpcode()) {
-  default:
-    return false;
-  case TargetOpcode::G_CONCAT_VECTORS: {
-    // Expecting exactly two FPTRUNCs
-    if (ParentDef->getNumOperands() != 3)
-      return false;
-
-    // All operands need to be FPTRUNC
-    for (unsigned OpIdx = 1, NumOperands = ParentDef->getNumOperands();
-         OpIdx != NumOperands; ++OpIdx) {
-      Register FpTruncDst = ParentDef->getOperand(OpIdx).getReg();
-      FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-
-      if (!isFPTruncFromDouble(MRI, FpTruncDef))
-        return false;
-    }
-
-    return true;
-  }
-  // This is to match cases in which vectors are widened to a larger size
-  case TargetOpcode::G_INSERT_VECTOR_ELT: {
-    Register VecExtractDst = ParentDef->getOperand(2).getReg();
-    MachineInstr *VecExtractDef = getDefIgnoringCopies(VecExtractDst, MRI);
-
-    if (!VecExtractDef ||
-        VecExtractDef->getOpcode() != TargetOpcode::G_EXTRACT_VECTOR_ELT)
-      return false;
-
-    Register FpTruncDst = VecExtractDef->getOperand(1).getReg();
-    FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-    break;
-  }
-  case TargetOpcode::G_FPTRUNC: {
-    Register FpTruncDst = ParentDef->getOperand(1).getReg();
-    FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-    break;
-  }
-  }
-
-  if (!isFPTruncFromDouble(MRI, FpTruncDef))
-    return false;
-
-  return true;
-}
-
-void applyFpTruncFpTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
-                         MachineIRBuilder &B) {
-  assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC && "Expected G_FPTRUNC");
-  Register Dst = MI.getOperand(0).getReg();
-  Register Src = MI.getOperand(1).getReg();
-
-  MachineInstr *ParentDef = getDefIgnoringCopies(Src, MRI);
-  if (!ParentDef)
-    return;
-
-  LLT V2F32 = LLT::fixed_vector(2, LLT::scalar(32));
-  LLT V4F32 = LLT::fixed_vector(4, LLT::scalar(32));
-  LLT V4F16 = LLT::fixed_vector(4, LLT::scalar(16));
-
-  B.setInstrAndDebugLoc(MI);
-
-  switch (ParentDef->getOpcode()) {
-  default:
-    return;
-  case TargetOpcode::G_INSERT_VECTOR_ELT: {
-    Register VecExtractDst = ParentDef->getOperand(2).getReg();
-    MachineInstr *VecExtractDef = getDefIgnoringCopies(VecExtractDst, MRI);
-
-    Register FpTruncDst = VecExtractDef->getOperand(1).getReg();
-    MachineInstr *FpTruncDef = getDefIgnoringCopies(FpTruncDst, MRI);
-
-    Register FpTruncSrc = FpTruncDef->getOperand(1).getReg();
-    MRI.setRegClass(FpTruncSrc, &AArch64::FPR128RegClass);
-
-    Register Fp32 = MRI.createGenericVirtualRegister(V2F32);
-    MRI.setRegClass(Fp32, &AArch64::FPR64RegClass);
-
-    B.buildInstr(AArch64::FCVTXNv2f32, {Fp32}, {FpTruncSrc});
-
-    // Only 4f32 -> 4f16 is legal so we need to mimic that situation
-    Register Fp32Padding = B.buildUndef(V2F32).getReg(0);
-    MRI.setRegClass(Fp32Padding, &AArch64::FPR64RegClass);
-
-    Register Fp32Full = MRI.createGenericVirtualRegister(V4F32);
-    MRI.setRegClass(Fp32Full, &AArch64::FPR128RegClass);
-    B.buildConcatVectors(Fp32Full, {Fp32, Fp32Padding});
-
-    Register Fp16 = MRI.createGenericVirtualRegister(V4F16);
-    MRI.setRegClass(Fp16, &AArch64::FPR64RegClass);
-    B.buildFPTrunc(Fp16, Fp32Full);
-
-    MRI.replaceRegWith(Dst, Fp16);
-    MI.eraseFromParent();
-    break;
-  }
-  case TargetOpcode::G_CONCAT_VECTORS: {
-    // Get the two FP Truncs that are being concatenated
-    Register FpTrunc1Dst = ParentDef->getOperand(1).getReg();
-    Register FpTrunc2Dst = ParentDef->getOperand(2).getReg();
-
-    MachineInstr *FpTrunc1Def = getDefIgnoringCopies(FpTrunc1Dst, MRI);
-    MachineInstr *FpTrunc2Def = getDefIgnoringCopies(FpTrunc2Dst, MRI);
-
-    // Make the registers 128bit to store the 2 doubles
-    Register LoFp64 = FpTrunc1Def->getOperand(1).getReg();
-    MRI.setRegClass(LoFp64, &AArch64::FPR128RegClass);
-    Register HiFp64 = FpTrunc2Def->getOperand(1).getReg();
-    MRI.setRegClass(HiFp64, &AArch64::FPR128RegClass);
-
-    // Convert the lower half
-    Register LoFp32 = MRI.createGenericVirtualRegister(V2F32);
-    MRI.setRegClass(LoFp32, &AArch64::FPR64RegClass);
-    B.buildInstr(AArch64::FCVTXNv2f32, {LoFp32}, {LoFp64});
-
-    // Create a register for the high half to use
-    Register AccUndef = MRI.createGenericVirtualRegister(V4F32);
-    MRI.setRegClass(AccUndef, &AArch64::FPR128RegClass);
-    B.buildUndef(AccUndef);
-
-    Register Acc = MRI.createGenericVirtualRegister(V4F32);
-    MRI.setRegClass(Acc, &AArch64::FPR128RegClass);
-    B.buildInstr(TargetOpcode::INSERT_SUBREG)
-        .addDef(Acc)
-        .addUse(AccUndef)
-        .addUse(LoFp32)
-        .addImm(AArch64::dsub);
-
-    // Convert the high half
-    Register AccOut = MRI.createGenericVirtualRegister(V4F32);
-    MRI.setRegClass(AccOut, &AArch64::FPR128RegClass);
-    B.buildInstr(AArch64::FCVTXNv4f32)
-        .addDef(AccOut)
-        .addUse(Acc)
-        .addUse(HiFp64);
-
-    Register Fp16 = MRI.createGenericVirtualRegister(V4F16);
-    MRI.setRegClass(Fp16, &AArch64::FPR64RegClass);
-    B.buildFPTrunc(Fp16, AccOut);
-
-    MRI.replaceRegWith(Dst, Fp16);
-    MI.eraseFromParent();
-    break;
-  }
-  }
-}
-
 /// \returns true if it would be profitable to swap the LHS and RHS of a G_ICMP
 /// instruction \p MI.
 bool trySwapICmpOperands(MachineInstr &MI, MachineRegisterInfo &MRI) {