Revert "[Mips] Support llvm.readcyclecounter intrinsic (#114953)"

This reverts commit 9cc7ee1.

Author: wzssyqa

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -357,10 +357,6 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
   setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
 
-  if (Subtarget.hasMips32r2() ||
-      getTargetMachine().getTargetTriple().isOSLinux())
-    setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
-
   // Lower fmin/fmax/fclass operations for MIPS R6.
   if (Subtarget.hasMips32r6()) {
     setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
@@ -1319,8 +1315,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
   case ISD::STORE:              return lowerSTORE(Op, DAG);
   case ISD::EH_DWARF_CFA:       return lowerEH_DWARF_CFA(Op, DAG);
   case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
-  case ISD::READCYCLECOUNTER:
-    return lowerREADCYCLECOUNTER(Op, DAG);
   }
   return SDValue();
 }
@@ -2102,44 +2096,6 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
   return exitMBB;
 }
 
-SDValue MipsTargetLowering::lowerREADCYCLECOUNTER(SDValue Op,
-                                                  SelectionDAG &DAG) const {
-  SmallVector<SDValue, 3> Results;
-  SDLoc DL(Op);
-  MachineFunction &MF = DAG.getMachineFunction();
-  unsigned RdhwrOpc, DestReg;
-  EVT PtrVT = getPointerTy(DAG.getDataLayout());
-
-  if (PtrVT == MVT::i64) {
-    RdhwrOpc = Mips::RDHWR64;
-    DestReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
-    SDNode *Rdhwr = DAG.getMachineNode(RdhwrOpc, DL, MVT::i64, MVT::Glue,
-                                       DAG.getRegister(Mips::HWR2, MVT::i32),
-                                       DAG.getTargetConstant(0, DL, MVT::i32));
-    SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, DestReg,
-                                     SDValue(Rdhwr, 0), SDValue(Rdhwr, 1));
-    SDValue ResNode =
-        DAG.getCopyFromReg(Chain, DL, DestReg, MVT::i64, Chain.getValue(1));
-    Results.push_back(ResNode);
-    Results.push_back(ResNode.getValue(1));
-  } else {
-    RdhwrOpc = Mips::RDHWR;
-    DestReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
-    SDNode *Rdhwr = DAG.getMachineNode(RdhwrOpc, DL, MVT::i32, MVT::Glue,
-                                       DAG.getRegister(Mips::HWR2, MVT::i32),
-                                       DAG.getTargetConstant(0, DL, MVT::i32));
-    SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, DestReg,
-                                     SDValue(Rdhwr, 0), SDValue(Rdhwr, 1));
-    SDValue ResNode =
-        DAG.getCopyFromReg(Chain, DL, DestReg, MVT::i32, Chain.getValue(1));
-    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResNode,
-                                  DAG.getConstant(0, DL, MVT::i32)));
-    Results.push_back(ResNode.getValue(1));
-  }
-
-  return DAG.getMergeValues(Results, DL);
-}
-
 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
   // The first operand is the chain, the second is the condition, the third is
   // the block to branch to if the condition is true.

llvm/lib/Target/Mips/MipsISelLowering.h

@@ -591,7 +591,6 @@ class TargetRegisterClass;
                                  bool IsSRA) const;
     SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
-    SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
 
     /// isEligibleForTailCallOptimization - Check whether the call is eligible
     /// for tail call optimization.