@@ -1255,8 +1255,9 @@ static bool isBFloat16Type(const SPIRVType *TypeDef) {
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}
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void addInstrRequirements (const MachineInstr &MI,
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- SPIRV::RequirementHandler &Reqs ,
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+ SPIRV::ModuleAnalysisInfo &MAI ,
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const SPIRVSubtarget &ST) {
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+ SPIRV::RequirementHandler &Reqs = MAI.Reqs ;
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switch (MI.getOpcode ()) {
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case SPIRV::OpMemoryModel: {
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int64_t Addr = MI.getOperand (0 ).getImm ();
@@ -1812,15 +1813,45 @@ void addInstrRequirements(const MachineInstr &MI,
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break ;
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case SPIRV::OpConvertHandleToImageINTEL:
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case SPIRV::OpConvertHandleToSamplerINTEL:
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- case SPIRV::OpConvertHandleToSampledImageINTEL:
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+ case SPIRV::OpConvertHandleToSampledImageINTEL: {
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if (!ST.canUseExtension (SPIRV::Extension::SPV_INTEL_bindless_images))
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report_fatal_error (" OpConvertHandleTo[Image/Sampler/SampledImage]INTEL "
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" instructions require the following SPIR-V extension: "
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" SPV_INTEL_bindless_images" ,
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false );
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+ SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry ();
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+ SPIRV::AddressingModel::AddressingModel AddrModel = MAI.Addr ;
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+ SPIRVType *TyDef = GR->getSPIRVTypeForVReg (MI.getOperand (1 ).getReg ());
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+ if (MI.getOpcode () == SPIRV::OpConvertHandleToImageINTEL &&
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+ TyDef->getOpcode () != SPIRV::OpTypeImage) {
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+ report_fatal_error (" Incorrect return type for the instruction "
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+ " OpConvertHandleToImageINTEL" ,
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+ false );
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+ } else if (MI.getOpcode () == SPIRV::OpConvertHandleToSamplerINTEL &&
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+ TyDef->getOpcode () != SPIRV::OpTypeSampler) {
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+ report_fatal_error (" Incorrect return type for the instruction "
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+ " OpConvertHandleToSamplerINTEL" ,
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+ false );
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+ } else if (MI.getOpcode () == SPIRV::OpConvertHandleToSampledImageINTEL &&
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+ TyDef->getOpcode () != SPIRV::OpTypeSampledImage) {
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+ report_fatal_error (" Incorrect return type for the instruction "
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+ " OpConvertHandleToSampledImageINTEL" ,
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+ false );
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+ }
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+ SPIRVType *SpvTy = GR->getSPIRVTypeForVReg (MI.getOperand (2 ).getReg ());
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+ unsigned Bitwidth = GR->getScalarOrVectorBitWidth (SpvTy);
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+ if (!(Bitwidth == 32 && AddrModel == SPIRV::AddressingModel::Physical32) &&
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+ !(Bitwidth == 64 && AddrModel == SPIRV::AddressingModel::Physical64)) {
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+ report_fatal_error (
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+ " Parameter value must be a 32-bit scalar in case of "
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+ " Physical32 addressing model or a 64-bit scalar in case of "
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+ " Physical64 addressing model" ,
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+ false );
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+ }
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Reqs.addExtension (SPIRV::Extension::SPV_INTEL_bindless_images);
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Reqs.addCapability (SPIRV::Capability::BindlessImagesINTEL);
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break ;
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+ }
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case SPIRV::OpSubgroup2DBlockLoadINTEL:
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case SPIRV::OpSubgroup2DBlockLoadTransposeINTEL:
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case SPIRV::OpSubgroup2DBlockLoadTransformINTEL:
@@ -1958,7 +1989,7 @@ static void collectReqs(const Module &M, SPIRV::ModuleAnalysisInfo &MAI,
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continue ;
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for (const MachineBasicBlock &MBB : *MF)
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for (const MachineInstr &MI : MBB)
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- addInstrRequirements (MI, MAI. Reqs , ST);
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+ addInstrRequirements (MI, MAI, ST);
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}
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// Collect requirements for OpExecutionMode instructions.
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auto Node = M.getNamedMetadata (" spirv.ExecutionMode" );
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