@@ -1676,6 +1676,7 @@ void VPIRMetadata::intersect(const VPIRMetadata &Other) {
16761676 Metadata = std::move (MetadataIntersection);
16771677}
16781678
1679+ #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
16791680void VPIRMetadata::print (raw_ostream &O, const Module *M) const {
16801681 if (Metadata.empty ())
16811682 return ;
@@ -1694,6 +1695,7 @@ void VPIRMetadata::print(raw_ostream &O, const Module *M) const {
16941695 });
16951696 O << " )" ;
16961697}
1698+ #endif
16971699
16981700void VPWidenCallRecipe::execute (VPTransformState &State) {
16991701 assert (State.VF .isVector () && " not widening" );
@@ -1991,6 +1993,8 @@ void VPWidenSelectRecipe::print(raw_ostream &O, const Twine &Indent,
19911993 O << " , " ;
19921994 getOperand (2 )->printAsOperand (O, SlotTracker);
19931995 O << (isInvariantCond () ? " (condition is loop invariant)" : " " );
1996+
1997+ VPIRMetadata::print (O, getParent ()->getPlan ()->getModule ());
19941998}
19951999#endif
19962000
@@ -3461,6 +3465,8 @@ void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent,
34613465
34623466 if (shouldPack ())
34633467 O << " (S->V)" ;
3468+
3469+ VPIRMetadata::print (O, getParent ()->getPlan ()->getModule ());
34643470}
34653471#endif
34663472
@@ -3727,6 +3733,7 @@ void VPWidenLoadEVLRecipe::print(raw_ostream &O, const Twine &Indent,
37273733 printAsOperand (O, SlotTracker);
37283734 O << " = vp.load " ;
37293735 printOperands (O, SlotTracker);
3736+ VPIRMetadata::print (O, getParent ()->getPlan ()->getModule ());
37303737}
37313738#endif
37323739
@@ -3835,6 +3842,7 @@ void VPWidenStoreEVLRecipe::print(raw_ostream &O, const Twine &Indent,
38353842 VPSlotTracker &SlotTracker) const {
38363843 O << Indent << " WIDEN vp.store " ;
38373844 printOperands (O, SlotTracker);
3845+ VPIRMetadata::print (O, getParent ()->getPlan ()->getModule ());
38383846}
38393847#endif
38403848
@@ -4123,6 +4131,8 @@ void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent,
41234131 }
41244132 ++OpIdx;
41254133 }
4134+
4135+ VPIRMetadata::print (O, getParent ()->getPlan ()->getModule ());
41264136}
41274137#endif
41284138
@@ -4267,6 +4277,8 @@ void VPInterleaveEVLRecipe::print(raw_ostream &O, const Twine &Indent,
42674277 }
42684278 ++OpIdx;
42694279 }
4280+
4281+ VPIRMetadata::print (O, getParent ()->getPlan ()->getModule ());
42704282}
42714283#endif
42724284
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