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‎llvm/include/llvm/CodeGen/SelectionDAG.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2322,6 +2322,10 @@ class SelectionDAG {
23222322
/// +nan are considered positive, -0.0, -inf and -nan are not.
23232323
LLVM_ABI bool cannotBeOrderedNegativeFP(SDValue Op) const;
23242324

2325+
/// Check if all uses of a floating-point value are insensitive to signed
2326+
/// zeros.
2327+
LLVM_ABI bool allUsesSignedZeroInsensitive(SDValue Op) const;
2328+
23252329
/// Test whether two SDValues are known to compare equal. This
23262330
/// is true if they are the same value, or if one is negative zero and the
23272331
/// other positive zero.

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 1 addition & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -18871,37 +18871,6 @@ SDValue DAGCombiner::visitFPOW(SDNode *N) {
1887118871

1887218872
return SDValue();
1887318873
}
18874-
/// Check if a use of a floating-point operation doesn't care about the sign of
18875-
/// zero. This allows us to optimize (sitofp (fptosi x)) -> ftrunc(x) even
18876-
/// without NoSignedZerosFPMath, as long as all uses are sign-insensitive.
18877-
static bool isSignInsensitiveUse(SDNode *Use, unsigned OperandNo,
18878-
SelectionDAG &DAG) {
18879-
switch (Use->getOpcode()) {
18880-
case ISD::SETCC:
18881-
// Comparisons: IEEE 754 specifies +0.0 == -0.0.
18882-
case ISD::FABS:
18883-
// fabs always produces +0.0.
18884-
return true;
18885-
case ISD::FADD:
18886-
case ISD::FSUB: {
18887-
// Arithmetic with non-zero constants fixes the uncertainty around the sign
18888-
// bit.
18889-
SDValue Other = Use->getOperand(1 - OperandNo);
18890-
return DAG.isKnownNeverZeroFloat(Other);
18891-
}
18892-
default:
18893-
return false;
18894-
}
18895-
}
18896-
18897-
/// Check if all uses of a value are insensitive to the sign of zero.
18898-
static bool allUsesSignInsensitive(SDValue V, SelectionDAG &DAG) {
18899-
return all_of(V->uses(), [&](SDUse &Use) {
18900-
SDNode *User = Use.getUser();
18901-
unsigned OperandNo = Use.getOperandNo();
18902-
return isSignInsensitiveUse(User, OperandNo, DAG);
18903-
});
18904-
}
1890518874

1890618875
static SDValue foldFPToIntToFP(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
1890718876
const TargetLowering &TLI) {
@@ -18924,7 +18893,7 @@ static SDValue foldFPToIntToFP(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
1892418893
assert(IsSigned || IsUnsigned);
1892518894

1892618895
bool IsSignedZeroSafe = DAG.getTarget().Options.NoSignedZerosFPMath ||
18927-
allUsesSignInsensitive(SDValue(N, 0), DAG);
18896+
DAG.allUsesSignedZeroInsensitive(SDValue(N, 0));
1892818897
// For signed conversions: The optimization changes signed zero behavior.
1892918898
if (IsSigned && !IsSignedZeroSafe)
1893018899
return SDValue();

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6075,6 +6075,35 @@ bool SelectionDAG::isKnownNeverZeroFloat(SDValue Op) const {
60756075
Op, [](ConstantFPSDNode *C) { return !C->isZero(); });
60766076
}
60776077

6078+
bool SelectionDAG::allUsesSignedZeroInsensitive(SDValue Op) const {
6079+
assert(Op.getValueType().isFloatingPoint());
6080+
return all_of(Op->uses(), [&](SDUse &Use) {
6081+
SDNode *User = Use.getUser();
6082+
unsigned OperandNo = Use.getOperandNo();
6083+
6084+
// Check if this use is insensitive to the sign of zero
6085+
switch (User->getOpcode()) {
6086+
case ISD::SETCC:
6087+
// Comparisons: IEEE-754 specifies +0.0 == -0.0.
6088+
case ISD::FABS:
6089+
// fabs always produces +0.0.
6090+
return true;
6091+
case ISD::FCOPYSIGN:
6092+
// copysign overwrites the sign bit of the first operand.
6093+
return OperandNo == 0;
6094+
case ISD::FADD:
6095+
case ISD::FSUB: {
6096+
// Arithmetic with non-zero constants fixes the uncertainty around the
6097+
// sign bit.
6098+
SDValue Other = User->getOperand(1 - OperandNo);
6099+
return isKnownNeverZeroFloat(Other);
6100+
}
6101+
default:
6102+
return false;
6103+
}
6104+
});
6105+
}
6106+
60786107
bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
60796108
if (Depth >= MaxRecursionDepth)
60806109
return false; // Limit search depth.

‎llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll‎

Lines changed: 52 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,48 @@ define i1 @test_fcmp(float %x) {
154154
ret i1 %cmp
155155
}
156156

157+
define float @test_fabs(float %x) {
158+
; CHECK-LABEL: test_fabs:
159+
; CHECK: // %bb.0:
160+
; CHECK-NEXT: frintz s0, s0
161+
; CHECK-NEXT: fabs s0, s0
162+
; CHECK-NEXT: ret
163+
;
164+
; NO-SIGNED-ZEROS-LABEL: test_fabs:
165+
; NO-SIGNED-ZEROS: // %bb.0:
166+
; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
167+
; NO-SIGNED-ZEROS-NEXT: fabs s0, s0
168+
; NO-SIGNED-ZEROS-NEXT: ret
169+
%conv1 = fptosi float %x to i32
170+
%conv2 = sitofp i32 %conv1 to float
171+
%abs = call float @llvm.fabs.f32(float %conv2)
172+
ret float %abs
173+
}
174+
175+
define float @test_copysign(float %x, float %y) {
176+
; CHECK-LABEL: test_copysign:
177+
; CHECK: // %bb.0:
178+
; CHECK-NEXT: frintz s0, s0
179+
; CHECK-NEXT: mvni v2.4s, #128, lsl #24
180+
; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
181+
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
182+
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
183+
; CHECK-NEXT: ret
184+
;
185+
; NO-SIGNED-ZEROS-LABEL: test_copysign:
186+
; NO-SIGNED-ZEROS: // %bb.0:
187+
; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
188+
; NO-SIGNED-ZEROS-NEXT: mvni v2.4s, #128, lsl #24
189+
; NO-SIGNED-ZEROS-NEXT: // kill: def $s1 killed $s1 def $q1
190+
; NO-SIGNED-ZEROS-NEXT: bif v0.16b, v1.16b, v2.16b
191+
; NO-SIGNED-ZEROS-NEXT: // kill: def $s0 killed $s0 killed $q0
192+
; NO-SIGNED-ZEROS-NEXT: ret
193+
%conv1 = fptosi float %x to i32
194+
%conv2 = sitofp i32 %conv1 to float
195+
%combine = call float @llvm.copysign.f32(float %conv2, float %y)
196+
ret float %combine
197+
}
198+
157199
define float @test_fadd(float %x) {
158200
; CHECK-LABEL: test_fadd:
159201
; CHECK: // %bb.0:
@@ -174,26 +216,29 @@ define float @test_fadd(float %x) {
174216
ret float %add
175217
}
176218

177-
define float @test_fabs(float %x) {
178-
; CHECK-LABEL: test_fabs:
219+
define float @test_fsub(float %x) {
220+
; CHECK-LABEL: test_fsub:
179221
; CHECK: // %bb.0:
180222
; CHECK-NEXT: frintz s0, s0
181-
; CHECK-NEXT: fabs s0, s0
223+
; CHECK-NEXT: fmov s1, #-1.00000000
224+
; CHECK-NEXT: fadd s0, s0, s1
182225
; CHECK-NEXT: ret
183226
;
184-
; NO-SIGNED-ZEROS-LABEL: test_fabs:
227+
; NO-SIGNED-ZEROS-LABEL: test_fsub:
185228
; NO-SIGNED-ZEROS: // %bb.0:
186229
; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
187-
; NO-SIGNED-ZEROS-NEXT: fabs s0, s0
230+
; NO-SIGNED-ZEROS-NEXT: fmov s1, #-1.00000000
231+
; NO-SIGNED-ZEROS-NEXT: fadd s0, s0, s1
188232
; NO-SIGNED-ZEROS-NEXT: ret
189233
%conv1 = fptosi float %x to i32
190234
%conv2 = sitofp i32 %conv1 to float
191-
%abs = call float @llvm.fabs.f32(float %conv2)
192-
ret float %abs
235+
%sub = fsub float %conv2, 1.0
236+
ret float %sub
193237
}
194238

195239
declare i32 @llvm.smin.i32(i32, i32)
196240
declare i32 @llvm.smax.i32(i32, i32)
197241
declare i32 @llvm.umin.i32(i32, i32)
198242
declare i32 @llvm.umax.i32(i32, i32)
199243
declare float @llvm.fabs.f32(float)
244+
declare float @llvm.copysign.f32(float, float)

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