[X86][APX] Compress setzucc with memory operand to setcc (#170842)

setzucc with memory operand is same as setcc but the later is shorter.

Author: fzou1

llvm/lib/Target/X86/X86CompressEVEX.cpp

@@ -15,6 +15,7 @@
 //   c. NDD (EVEX) -> non-NDD (legacy)
 //   d. NF_ND (EVEX) -> NF (EVEX)
 //   e. NonNF (EVEX) -> NF (EVEX)
+//   f. SETZUCCm (EVEX) -> SETCCm (legacy)
 //
 // Compression a, b and c can always reduce code size, with some exceptions
 // such as promoted 16-bit CRC32 which is as long as the legacy version.
@@ -216,14 +217,15 @@ static bool CompressEVEXImpl(MachineInstr &MI, MachineBasicBlock &MBB,
   //  memory form: broadcast
   //
   // APX:
-  //  MAP4: NDD
+  //  MAP4: NDD, ZU
   //
   // For AVX512 cases, EVEX prefix is needed in order to carry this information
   // thus preventing the transformation to VEX encoding.
   bool IsND = X86II::hasNewDataDest(TSFlags);
-  if (TSFlags & X86II::EVEX_B && !IsND)
-    return false;
   unsigned Opc = MI.getOpcode();
+  bool IsSetZUCCm = Opc == X86::SETZUCCm;
+  if (TSFlags & X86II::EVEX_B && !IsND && !IsSetZUCCm)
+    return false;
   // MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
   bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr;
   bool IsRedundantNDD = IsNDLike ? IsRedundantNewDataDest(Opc) : false;
@@ -339,7 +341,7 @@ bool CompressEVEXPass::runOnMachineFunction(MachineFunction &MF) {
   }
 #endif
   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
-  if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD())
+  if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD() && !ST.hasZU())
     return false;
 
   bool Changed = false;

llvm/test/CodeGen/X86/apx/compress-evex.mir

@@ -139,3 +139,11 @@ body:             |
     $ax = XOR16rr_ND $ax, killed $di, implicit-def dead $eflags
     RET64 $rax
 ...
+---
+name:            setzuccm_2_setccm
+body:             |
+  bb.0.entry:
+  liveins: $eflags
+  ; CHECK: sete 7(%rsp)  # EVEX TO LEGACY Compression encoding: [0x0f,0x94,0x44,0x24,0x07]
+    SETZUCCm $rsp, 1, $noreg, 7, $noreg, 4, implicit killed $eflags
+...

llvm/test/TableGen/x86-instr-mapping.inc

@@ -158,6 +158,7 @@ static const X86TableEntry X86CompressEVEXTable[] = {
   { X86::SARX32rr_EVEX, X86::SARX32rr },
   { X86::SARX64rm_EVEX, X86::SARX64rm },
   { X86::SARX64rr_EVEX, X86::SARX64rr },
+  { X86::SETZUCCm, X86::SETCCm },
   { X86::SHLX32rm_EVEX, X86::SHLX32rm },
   { X86::SHLX32rr_EVEX, X86::SHLX32rr },
   { X86::SHLX64rm_EVEX, X86::SHLX64rm },

llvm/utils/TableGen/X86InstrMappingEmitter.cpp

@@ -189,13 +189,14 @@ void X86InstrMappingEmitter::emitCompressEVEXTable(
     RecognizableInstrBase RI(*Inst);
 
     bool IsND = RI.OpMap == X86Local::T_MAP4 && RI.HasEVEX_B && RI.HasVEX_4V;
+    bool IsSETZUCCm = Name == "SETZUCCm";
     // Add VEX encoded instructions to one of CompressedInsts vectors according
     // to it's opcode.
     if (RI.Encoding == X86Local::VEX)
       CompressedInsts[RI.Opcode].push_back(Inst);
     // Add relevant EVEX encoded instructions to PreCompressionInsts
     else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 &&
-             (!RI.HasEVEX_B || IsND))
+             (!RI.HasEVEX_B || IsND || IsSETZUCCm))
       PreCompressionInsts.push_back(Inst);
   }
 

llvm/utils/TableGen/X86ManualInstrMapping.def

@@ -333,6 +333,7 @@ ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDYrm)
 ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDYrr)
 ENTRY(VPBROADCASTQZ256rm, VPBROADCASTQYrm)
 ENTRY(VPBROADCASTQZ256rr, VPBROADCASTQYrr)
+ENTRY(SETZUCCm, SETCCm)
 #undef ENTRY
 
 #ifndef NOCOMP_ND