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alexey-bataevalexey-bataev
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[SLP][NFC]Remove undef and update tests
1 parent c9a5a6d commit 0e11e19

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+41
-41
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2 files changed

+41
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‎llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -12,67 +12,67 @@
1212
; iteration (it was matched and vectorized, which added a use of a deleted
1313
; instruction)
1414

15-
define void @test(i1 %arg) {
15+
define void @test(i1 %arg, ptr %p) {
1616
; CHECK-LABEL: @test(
1717
; CHECK-NEXT: entry:
1818
; CHECK-NEXT: br i1 %arg, label [[IF_END:%.*]], label [[FOR_COND_PREHEADER:%.*]]
1919
; CHECK: for.cond.preheader:
20-
; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [100 x i32], ptr undef, i64 0, i64 2
21-
; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds [100 x i32], ptr undef, i64 0, i64 3
20+
; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 2
21+
; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 3
2222
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[I]], align 8
2323
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP0]])
24-
; CHECK-NEXT: [[OP_RDX3:%.*]] = add i32 [[TMP1]], undef
24+
; CHECK-NEXT: [[OP_RDX3:%.*]] = add i32 [[TMP1]], 0
2525
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[I1]], align 4
2626
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
27-
; CHECK-NEXT: [[OP_RDX2:%.*]] = add i32 [[TMP3]], undef
27+
; CHECK-NEXT: [[OP_RDX2:%.*]] = add i32 [[TMP3]], 0
2828
; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[OP_RDX3]], 2
29-
; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 undef, [[TMP4]]
29+
; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 0, [[TMP4]]
3030
; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[OP_RDX2]], 2
3131
; CHECK-NEXT: [[OP_RDX1:%.*]] = add i32 [[OP_RDX]], [[TMP5]]
3232
; CHECK-NEXT: br label [[IF_END]]
3333
; CHECK: if.end:
34-
; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[OP_RDX1]], [[FOR_COND_PREHEADER]] ], [ undef, [[ENTRY:%.*]] ]
34+
; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[OP_RDX1]], [[FOR_COND_PREHEADER]] ], [ 0, [[ENTRY:%.*]] ]
3535
; CHECK-NEXT: ret void
3636
;
3737
entry:
3838
br i1 %arg, label %if.end, label %for.cond.preheader
3939

4040
for.cond.preheader: ; preds = %entry
41-
%i = getelementptr inbounds [100 x i32], ptr undef, i64 0, i64 2
42-
%i1 = getelementptr inbounds [100 x i32], ptr undef, i64 0, i64 3
43-
%i2 = getelementptr inbounds [100 x i32], ptr undef, i64 0, i64 4
44-
%i3 = getelementptr inbounds [100 x i32], ptr undef, i64 0, i64 5
45-
%i4 = getelementptr inbounds [100 x i32], ptr undef, i64 0, i64 6
41+
%i = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 2
42+
%i1 = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 3
43+
%i2 = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 4
44+
%i3 = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 5
45+
%i4 = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 6
4646
%ld0 = load i32, ptr %i, align 8
4747
%ld1 = load i32, ptr %i1, align 4
4848
%ld2 = load i32, ptr %i2, align 16
4949
%ld3 = load i32, ptr %i3, align 4
50-
%i5 = add i32 undef, undef
50+
%i5 = add i32 0, 0
5151
%i6 = add i32 %i5, %ld3
5252
%i7 = add i32 %i6, %ld2
5353
%i8 = add i32 %i7, %ld1
5454
%i9 = add i32 %i8, %ld0
55-
%i10 = add i32 %i9, undef
55+
%i10 = add i32 %i9, 0
5656
%i11 = add i32 %i9, %i10
5757
%ld4 = load i32, ptr %i1, align 4
5858
%ld5 = load i32, ptr %i2, align 16
5959
%ld6 = load i32, ptr %i3, align 4
6060
%ld7 = load i32, ptr %i4, align 8
61-
%i12 = add i32 undef, undef
61+
%i12 = add i32 0, 0
6262
%i13 = add i32 %i12, %ld7
6363
%i14 = add i32 %i13, %ld6
6464
%i15 = add i32 %i14, %ld5
6565
%i16 = add i32 %i15, %ld4
66-
%i17 = add i32 %i16, undef
66+
%i17 = add i32 %i16, 0
6767
%i18 = add i32 %i17, %i11
6868
%i19 = add i32 %i17, %i18
69-
%i20 = add i32 undef, %i19
70-
%i21 = add i32 undef, %i20
71-
%i22 = add i32 undef, %i21
72-
%i23 = add i32 undef, %i22
69+
%i20 = add i32 0, %i19
70+
%i21 = add i32 0, %i20
71+
%i22 = add i32 0, %i21
72+
%i23 = add i32 0, %i22
7373
br label %if.end
7474

7575
if.end: ; preds = %for.cond.preheader, %entry
76-
%r = phi i32 [ %i23, %for.cond.preheader ], [ undef, %entry ]
76+
%r = phi i32 [ %i23, %for.cond.preheader ], [ 0, %entry ]
7777
ret void
7878
}

‎llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -3,55 +3,55 @@
33

44
%"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76" = type { i32, i32 }
55

6-
define void @_Z2azv() local_unnamed_addr {
6+
define void @_Z2azv(ptr %p) local_unnamed_addr {
77
; CHECK-LABEL: @_Z2azv(
88
; CHECK-NEXT: for.body.lr.ph:
9-
; CHECK-NEXT: [[DOTSROA_CAST_4:%.*]] = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 4, i32 0
9+
; CHECK-NEXT: [[DOTSROA_CAST_4:%.*]] = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr [[P:%.*]], i64 4, i32 0
1010
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[DOTSROA_CAST_4]], align 4
1111
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP1]])
12-
; CHECK-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP2]], undef
13-
; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP2]], i32 undef
14-
; CHECK-NEXT: [[DOTSROA_SPECULATED_9:%.*]] = select i1 undef, i32 undef, i32 [[OP_RDX1]]
15-
; CHECK-NEXT: [[CMP_I1_10:%.*]] = icmp slt i32 [[DOTSROA_SPECULATED_9]], undef
12+
; CHECK-NEXT: [[OP_RDX:%.*]] = icmp sgt i32 [[TMP2]], 0
13+
; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP2]], i32 0
14+
; CHECK-NEXT: [[DOTSROA_SPECULATED_9:%.*]] = select i1 false, i32 0, i32 [[OP_RDX1]]
15+
; CHECK-NEXT: [[CMP_I1_10:%.*]] = icmp slt i32 [[DOTSROA_SPECULATED_9]], 0
1616
; CHECK-NEXT: ret void
1717
;
1818
for.body.lr.ph:
19-
%.sroa_cast.4 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 4, i32 0
19+
%.sroa_cast.4 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 4, i32 0
2020
%retval.sroa.0.0.copyload.i5.4 = load i32, ptr %.sroa_cast.4, align 4
21-
%.sroa_raw_idx.4 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 4, i32 1
21+
%.sroa_raw_idx.4 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 4, i32 1
2222
%retval.sroa.0.0.copyload.i7.4 = load i32, ptr %.sroa_raw_idx.4, align 4
2323
%cmp.i2.4 = icmp slt i32 %retval.sroa.0.0.copyload.i5.4, %retval.sroa.0.0.copyload.i7.4
2424
%0 = select i1 %cmp.i2.4, i32 %retval.sroa.0.0.copyload.i7.4, i32 %retval.sroa.0.0.copyload.i5.4
25-
%cmp.i1.4 = icmp slt i32 undef, %0
26-
%.sroa.speculated.4 = select i1 %cmp.i1.4, i32 %0, i32 undef
27-
%.sroa_cast.5 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 5, i32 0
25+
%cmp.i1.4 = icmp slt i32 0, %0
26+
%.sroa.speculated.4 = select i1 %cmp.i1.4, i32 %0, i32 0
27+
%.sroa_cast.5 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 5, i32 0
2828
%retval.sroa.0.0.copyload.i5.5 = load i32, ptr %.sroa_cast.5, align 4
29-
%.sroa_raw_idx.5 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 5, i32 1
29+
%.sroa_raw_idx.5 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 5, i32 1
3030
%retval.sroa.0.0.copyload.i7.5 = load i32, ptr %.sroa_raw_idx.5, align 4
3131
%cmp.i2.5 = icmp slt i32 %retval.sroa.0.0.copyload.i5.5, %retval.sroa.0.0.copyload.i7.5
3232
%1 = select i1 %cmp.i2.5, i32 %retval.sroa.0.0.copyload.i7.5, i32 %retval.sroa.0.0.copyload.i5.5
3333
%cmp.i1.5 = icmp slt i32 %.sroa.speculated.4, %1
3434
%.sroa.speculated.5 = select i1 %cmp.i1.5, i32 %1, i32 %.sroa.speculated.4
35-
%.sroa_cast.6 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 6, i32 0
35+
%.sroa_cast.6 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 6, i32 0
3636
%retval.sroa.0.0.copyload.i5.6 = load i32, ptr %.sroa_cast.6, align 4
37-
%.sroa_raw_idx.6 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 6, i32 1
37+
%.sroa_raw_idx.6 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 6, i32 1
3838
%retval.sroa.0.0.copyload.i7.6 = load i32, ptr %.sroa_raw_idx.6, align 4
3939
%cmp.i2.6 = icmp slt i32 %retval.sroa.0.0.copyload.i5.6, %retval.sroa.0.0.copyload.i7.6
4040
%2 = select i1 %cmp.i2.6, i32 %retval.sroa.0.0.copyload.i7.6, i32 %retval.sroa.0.0.copyload.i5.6
4141
%cmp.i1.6 = icmp slt i32 %.sroa.speculated.5, %2
4242
%.sroa.speculated.6 = select i1 %cmp.i1.6, i32 %2, i32 %.sroa.speculated.5
43-
%.sroa_cast.7 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 7, i32 0
43+
%.sroa_cast.7 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 7, i32 0
4444
%retval.sroa.0.0.copyload.i5.7 = load i32, ptr %.sroa_cast.7, align 4
45-
%.sroa_raw_idx.7 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr undef, i64 7, i32 1
45+
%.sroa_raw_idx.7 = getelementptr inbounds %"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76", ptr %p, i64 7, i32 1
4646
%retval.sroa.0.0.copyload.i7.7 = load i32, ptr %.sroa_raw_idx.7, align 4
4747
%cmp.i2.7 = icmp slt i32 %retval.sroa.0.0.copyload.i5.7, %retval.sroa.0.0.copyload.i7.7
4848
%3 = select i1 %cmp.i2.7, i32 %retval.sroa.0.0.copyload.i7.7, i32 %retval.sroa.0.0.copyload.i5.7
4949
%cmp.i1.7 = icmp slt i32 %.sroa.speculated.6, %3
5050
%.sroa.speculated.7 = select i1 %cmp.i1.7, i32 %3, i32 %.sroa.speculated.6
51-
%cmp.i1.8 = icmp slt i32 %.sroa.speculated.7, undef
52-
%.sroa.speculated.8 = select i1 %cmp.i1.8, i32 undef, i32 %.sroa.speculated.7
53-
%.sroa.speculated.9 = select i1 undef, i32 undef, i32 %.sroa.speculated.8
54-
%cmp.i1.10 = icmp slt i32 %.sroa.speculated.9, undef
51+
%cmp.i1.8 = icmp slt i32 %.sroa.speculated.7, 0
52+
%.sroa.speculated.8 = select i1 %cmp.i1.8, i32 0, i32 %.sroa.speculated.7
53+
%.sroa.speculated.9 = select i1 0, i32 0, i32 %.sroa.speculated.8
54+
%cmp.i1.10 = icmp slt i32 %.sroa.speculated.9, 0
5555
ret void
5656
}
5757

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